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Merge branch 'jalr-invalid-instruction' into 'master'

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Trigger an invalid instruction if jalr op code bits 14:12 are not zero

According to the RISC-V ISA specification 2.1 the bits 15:12 of the `jalr` instruction should be zero. The decoder stage of checks that and aborts the jump if so. However, this is an invalid instruction, which should be signaled.

/cc @pasquale.schiavone 

See merge request !1
This commit is contained in:
Pasquale Davide Schiavone 2016-06-15 09:33:44 +02:00
commit 11aa315721
1 changed files with 1 additions and 1 deletions
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decoder.sv
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@ -221,7 +221,7 @@ module riscv_decoder
if (instr_rdata_i[14:12] != 3'b0) begin if (instr_rdata_i[14:12] != 3'b0) begin
jump_in_id = BRANCH_NONE; jump_in_id = BRANCH_NONE;
regfile_alu_we = 1'b0; regfile_alu_we = 1'b0;
illegal_insn_o = 1'b0; illegal_insn_o = 1'b1;
end end
end end