[simple-system] always_comb should be always

Previous lint fix was incorrect. The 'always_comb' block here should be
an 'always'. It is not combinational logic but rather an infinite loop
to generate a clock when running in a simulator that isn't verilator
(e.g.  under simple-system under VCS) so the use of 'always' is
appropriate.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

examples/simple_system/rtl/ibex_simple_system.sv

@@ -119,7 +119,7 @@ module ibex_simple_system (
       #8
       rst_sys_n = 1'b1;
     end
-    always_comb begin
+    always begin
       #1 clk_sys = 1'b0;
       #1 clk_sys = 1'b1;
     end