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[dv] Fix Xcelium compilation

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Need these fixes in order to pass Xcelium compile in OpenTitan

Signed-off-by: Weicai Yang <weicai@google.com>
This commit is contained in:
Weicai 2020-04-17 11:43:38 -07:00 • committed by Philipp Wagner
parent eb4913c8f0
commit 1b024135c7
3 changed files with 10 additions and 4 deletions
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4
shared/rtl/bus.sv
View file

@ -15,8 +15,8 @@
* - Host (master) arbitration is strictly priority based.
*/
module bus #(
parameter NrDevices,
parameter NrHosts,
parameter NrDevices = 1,
parameter NrHosts = 1,
parameter DataWidth = 32,
parameter AddressWidth = 32
) (

5
shared/rtl/ram_1p.sv
View file

@ -5,6 +5,9 @@
/**
* Single-port RAM with 1 cycle read/write delay, 32 bit words
*/
`include "prim_assert.sv"
module ram_1p #(
parameter int Depth = 128
) (
@ -75,7 +78,7 @@ module ram_1p #(
`endif
`ifdef SRAM_INIT_FILE
localparam MEM_FILE = `"`SRAM_INIT_FILE`";
localparam MEM_FILE = `PRIM_STRINGIFY(`SRAM_INIT_FILE);
initial begin
$display("Initializing SRAM from %s", MEM_FILE);
$readmemh(MEM_FILE, mem);

5
shared/rtl/ram_2p.sv
View file

@ -12,6 +12,9 @@
* Simultaneous write operations by both ports to the same address are to be avoided: The data
* written to memory is not determined.
*/
`include "prim_assert.sv"
module ram_2p #(
parameter int Depth = 128
) (
@ -116,7 +119,7 @@ module ram_2p #(
`endif
`ifdef SRAM_INIT_FILE
localparam MEM_FILE = `"`SRAM_INIT_FILE`";
localparam MEM_FILE = `PRIM_STRINGIFY(`SRAM_INIT_FILE);
initial begin
$display("Initializing SRAM from %s", MEM_FILE);
$readmemh(MEM_FILE, mem);