github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-22 21:17:59 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Add fence instruction to tracer (#134)

Browse source
This commit is contained in:
Tobias Wölfel 2019-07-11 09:59:28 +02:00 • committed by Philipp Wagner
parent edccb325e4
commit 1df87f4400
3 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
examples/sim/tb/ibex_tracer_tb.sv
View file

@ -40,8 +40,11 @@ module ibex_tracer_tb;
#10ns instr_rdata = 32'h60008113;
#10ns instr_rdata = 32'h00000013;
#10ns instr_rdata = 32'h00000113;
#30ns instr_rdata = 32'h00000013;
#10ns instr_rdata = 32'h0000000f;
#10ns instr_rdata = 32'h00000013;
#10ns instr_rdata = 32'h00000013;
#10ns instr_rdata = 32'h0000000f;
end
ibex_core_tracer ibex_i (

2
rtl/ibex_tracer.sv
View file

@ -395,6 +395,8 @@ module ibex_tracer #(
// LOAD & STORE
INSTR_LOAD: trace.printLoadInstr();
INSTR_STORE: trace.printStoreInstr();
// MISC-MEM
INSTR_FENCE: trace.printMnemonic("fence");
default: trace.printMnemonic("INVALID");
endcase // unique case (instr_i)
end

3
rtl/ibex_tracer_defines.sv
View file

@ -68,4 +68,7 @@ parameter logic [31:0] INSTR_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCOD
parameter logic [31:0] INSTR_LOAD = {25'b?, {OPCODE_LOAD } };
parameter logic [31:0] INSTR_STORE = {25'b?, {OPCODE_STORE} };
// MISC-MEM
parameter logic [31:0] INSTR_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
endpackage