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Make dummy clock gating module compatible with latch-based reg file

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The latch-based register file needs a clock gating cell that is
transparent for the clock enable signal only during the low clock
phase.
This commit is contained in:
Pirmin Vogel 2019-06-25 15:14:52 +01:00
parent 89b0d3a200
commit 2ed71a499a
1 changed files with 10 additions and 2 deletions
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12
dv/uvm/tb/prim_clock_gating.sv
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@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Dummy clock gating module
// Dummy clock gating module compatible with latch-based register file
module prim_clock_gating #(
parameter Impl = "default"
@ -13,6 +13,14 @@ module prim_clock_gating #(
output logic clk_o
);
assign clk_o = en_i ? clk_i : 0;
logic clk_en;
always_latch begin
if (clk_i == 1'b0) begin
clk_en <= en_i | test_en_i;
end
end
assign clk_o = clk_i & clk_en;
endmodule