Remove TCDM_ADDR_PRECAL and some other cleanup

alu.sv

@@ -48,11 +48,7 @@ module alu
 );
 
 
-`ifdef TCDM_ADDR_PRECAL
-  assign adder_lsu_o = adder_i;
-`else
   assign adder_lsu_o = operand_a_i + operand_b_i;
-`endif
 
   logic [31:0] operand_a_rev;     // bit reversed signal of operand_a_i
 

ex_stage.sv

@@ -96,11 +96,6 @@ module ex_stage
     // To IF: Jump and branch target and decision
     output logic [31:0]               jump_target_o,
     output logic                      branch_decision_o
-
-`ifdef TCDM_ADDR_PRECAL
-    ,
-    input logic [31:0]                alu_adder_i
-`endif
 );
 
 
@@ -125,19 +120,16 @@ module ex_stage
     if (csr_access_i == 1'b1)
       regfile_alu_wdata_fw_o = csr_rdata_i;
   end
-  // assign regfile_alu_wdata_fw_o    = (mult_en_i == 1'b0) ? alu_result : mult_result;
 
-  //NOTE Igor fix: replaced alu_adder_int with alu_adder_lsu_int --> Now data_addr is calculated with
-  //NOTE a dedicated adder, no carry is considered , just op_a + op_b from id stage
-  assign data_addr_ex_o        = (prepost_useincr_i == 1'b1) ? alu_adder_lsu_int : alu_operand_a_i;
+  assign data_addr_ex_o = (prepost_useincr_i == 1'b1) ? alu_adder_lsu_int : alu_operand_a_i;
 
   // hwloop mux. selects the right data to be sent to the hwloop registers (start/end-address and counter)
   always_comb
   begin : hwloop_start_mux
     case (hwloop_wb_mux_sel_i)
-      1'b0: hwloop_start_data_o  = hwloop_pc_plus4_i;
-      1'b1: hwloop_start_data_o  = alu_result;
-    endcase; // case (hwloop_wb_mux_sel)
+      1'b0: hwloop_start_data_o = hwloop_pc_plus4_i;
+      1'b1: hwloop_start_data_o = alu_result;
+    endcase
   end
 
   // assign alu result to hwloop end data
@@ -146,7 +138,7 @@ module ex_stage
   // assign hwloop mux. selects the right data to be sent to the hwloop registers (start/end-address and counter)
   assign hwloop_cnt_data_o = hwloop_cnt_i;
 
-  // Branch is taken when result == 1'b1
+  // Branch is taken when result[0] == 1'b1
   assign branch_decision_o = alu_result[0];
   assign jump_target_o     = alu_operand_c_i;
 

id_stage.sv

@@ -148,10 +148,6 @@ module id_stage
     input  logic        regfile_alu_we_fw_i,
     input  logic [31:0] regfile_alu_wdata_fw_i,
 
-`ifdef TCDM_ADDR_PRECAL
-    output logic [31:0] alu_adder_o,
-`endif
-
     // Performance Counters
     output logic        perf_jump_o,          // we are executing a jump instruction   (j, jr, jal, jalr)
     output logic        perf_branch_o,        // we are executing a branch instruction (bf, bnf)
@@ -787,10 +783,6 @@ module id_stage
 
       jump_in_ex                  <= 2'b0;
 
-      `ifdef TCDM_ADDR_PRECAL
-      alu_adder_o                 <= '0;
-      `endif
-
     end
     else if ((stall_ex_o == 1'b0) && (data_misaligned_i == 1'b1))
     begin // misaligned access case, only unstall alu operands
@@ -854,10 +846,6 @@ module id_stage
 
       jump_in_ex                  <= jump_in_id_o;
 
-`ifdef TCDM_ADDR_PRECAL
-      alu_adder_o                 <= alu_operand_a + alu_operand_b;
-`endif
-
     end
   end
 

include/defines.sv

@@ -380,9 +380,14 @@ endfunction // prettyPrintInstruction
 `define EXC_CAUSE_ECALL  {1'b0, 4'd11};
 `define EXC_CAUSE_EBREAK {1'b0, 4'd03};
 
-// Hardware loops
+
+// Hardware loop registers
+// Caution: Changing this parameter is not sufficient to increase the number of
+// hwloop registers! There are adjustments needed in hwloop_controller and
+// controller (decoder).
 `define HWLOOP_REGS 2
 
+
 // Debug module
 `define N_WP      2     // #Watchpoints
 `define DCR_DP    0
@@ -398,10 +403,6 @@ endfunction // prettyPrintInstruction
 `define DSR_INTE  1
 
 
-
-// TCDM_ADDRES PRE CALCULATION --> Bring part of the alu_adder_o calculation in the ID stage
-//`define TCDM_ADDR_PRECAL
-
 //`define BRANCH_PREDICTION
 
 `endif

riscv_core.sv

@@ -222,10 +222,6 @@ module riscv_core
   logic [31:0] dbg_npc;
   logic        dbg_set_npc;
 
-`ifdef TCDM_ADDR_PRECAL
-  logic [31:0] alu_adder_ex;
-`endif
-
   // Performance Counters
   logic        perf_jump;
   logic        perf_branch;
@@ -421,9 +417,6 @@ module riscv_core
       .regfile_waddr_wb_i           ( regfile_waddr_fw_wb_o         ),  // Write address ex-wb pipeline
       .regfile_we_wb_i              ( regfile_we_wb                 ),  // write enable for the register file
       .regfile_wdata_wb_i           ( regfile_wdata                 ),  // write data to commit in the register file
-`ifdef TCDM_ADDR_PRECAL
-      .alu_adder_o                  ( alu_adder_ex                  ),
-`endif
 
       .perf_jump_o                  ( perf_jump                     ),
       .perf_branch_o                ( perf_branch                   ),
@@ -506,11 +499,6 @@ module riscv_core
       .regfile_alu_waddr_fw_o     ( regfile_alu_waddr_fw         ),
       .regfile_alu_we_fw_o        ( regfile_alu_we_fw            ),
       .regfile_alu_wdata_fw_o     ( regfile_alu_wdata_fw         )
-
-`ifdef TCDM_ADDR_PRECAL
-      ,
-      .alu_adder_i                ( alu_adder_ex                 )
-`endif
     );