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https://github.com/openhwgroup/cve2.git
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Reimplemented jumps/branches in a more intelligent way; prevent forwarding of x0
This commit is contained in:
Sven Stucki
parent
10d9a75f27
commit
43ccb41536
6 changed files with 48 additions and 14 deletions
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@ -299,6 +299,13 @@ module controller
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ctrl_fsm_ns = DECODE;
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end
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// Store core ID in x18 (a0) // TODO: Temporary hack
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alu_op_a_mux_sel_o = `OP_A_ZERO;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_CID;
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alu_operator = `ALU_ADD;
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regfile_alu_we = 1'b1;
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// hwloop detected, jump to start address!
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// Attention: This has to be done in the DECODE and the FIRST_FETCH states
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if (hwloop_jump_i == 1'b1)
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@ -1226,7 +1233,10 @@ module controller
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// Jump and Branch handling //
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////////////////////////////////////////////////////////////////////////////////////////////
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//assign force_nop_o = (jump_in_id_o != 2'b00)? 1'b1 : 1'b0;
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assign force_nop_o = (jump_in_id_o != 2'b00 || jump_in_ex_i != 2'b00)? 1'b1 : 1'b0;
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//assign force_nop_o = (!instr_ack_stall && (jump_in_id_o != 2'b00 || jump_in_ex_i != 2'b00))? 1'b1 : 1'b0;
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//assign force_nop_o = (!stall_ex_o && jump_in_id_o == 2'b01)? 1'b1 : 1'b0;
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assign drop_instruction_o = 1'b0;
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////////////////////////////////////////////////////////////////////////////////////////////
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@ -1237,8 +1247,8 @@ module controller
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// we unstall the if_stage if the debug unit wants to set a new
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// pc, so that the new value gets written into current_pc_if and is
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// used by the instr_core_interface
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stall_if_o = (instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i | (~pc_valid_i));
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stall_id_o = instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i;
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stall_if_o = instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i | (~pc_valid_i);
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stall_id_o = instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i;
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stall_ex_o = instr_ack_stall | lsu_stall | dbg_stall_i;
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stall_wb_o = lsu_stall | dbg_stall_i;
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end
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@ -1293,6 +1303,12 @@ module controller
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operand_a_fw_mux_sel_o = `SEL_FW_EX;
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operand_b_fw_mux_sel_o = `SEL_REGFILE;
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end
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// Make sure x0 is never forwarded
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if (instr_rdata_i[`REG_S1] == 5'b0)
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operand_a_fw_mux_sel_o = `SEL_REGFILE;
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if (instr_rdata_i[`REG_S2] == 5'b0)
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operand_b_fw_mux_sel_o = `SEL_REGFILE;
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end
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// update registers
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@ -126,7 +126,7 @@ module ex_stage
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// To IF: Jump and branch target and decision
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output logic [31:0] jump_target_o,
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output logic [1:0] jump_in_ex_o,
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//output logic [1:0] jump_in_ex_o,
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output logic branch_decision_o
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`ifdef TCDM_ADDR_PRECAL
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@ -269,7 +269,7 @@ module ex_stage
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regfile_rb_data_wb_o <= 32'h0000_0000;
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sp_we_wb_o <= 1'b0;
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eoc_o <= 1'b0;
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jump_in_ex_o <= '0;
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//jump_in_ex_o <= '0;
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end
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else
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begin
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@ -282,7 +282,7 @@ module ex_stage
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regfile_rb_data_wb_o <= regfile_rb_data_i;
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sp_we_wb_o <= sp_we_i;
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eoc_o <= eoc_i;
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jump_in_ex_o <= jump_in_id_i;
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//jump_in_ex_o <= jump_in_id_i;
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end
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end
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end
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16
id_stage.sv
16
id_stage.sv
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@ -38,6 +38,8 @@ module id_stage
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input logic clk,
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input logic rst_n,
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input logic [4:0] core_id_i,
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input logic fetch_enable_i,
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output logic core_busy_o,
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@ -49,7 +51,8 @@ module id_stage
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// Jumps and branches
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output logic [1:0] jump_in_id_o,
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input logic [1:0] jump_in_ex_i,
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//input logic [1:0] jump_in_ex_i,
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output logic [1:0] jump_in_ex_o,
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// IF and ID stage signals
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//output logic [31:0] pc_from_immediate_o, // TODO: remove
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@ -197,7 +200,9 @@ module id_stage
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// Signals running between controller and exception controller
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//logic jump_in_id;
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//logic jump_in_ex; // registered copy of jump_in_id
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logic jump_in_ex; // registered copy of jump_in_id
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assign jump_in_ex_o = jump_in_ex;
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logic illegal_insn;
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logic trap_insn;
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logic pipe_flush;
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@ -453,6 +458,7 @@ module id_stage
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`IMM_S: immediate_b = imm_s_type;
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`IMM_U: immediate_b = imm_u_type;
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`IMM_HEX4: immediate_b = 32'h4;
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`IMM_CID: immediate_b = core_id_i; // TODO: Temporary hack
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default: immediate_b = 32'h4;
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endcase; // case (immediate_mux_sel)
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end
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@ -676,7 +682,7 @@ module id_stage
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.operand_c_fw_mux_sel_o ( operand_c_fw_mux_sel ),
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// To controller (TODO: Remove when control/decode separated and moved)
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.jump_in_ex_i ( jump_in_ex_i ),
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.jump_in_ex_i ( jump_in_ex_o ),
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// To EX: Jump/Branch indication
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.jump_in_id_o ( jump_in_id_o ),
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@ -841,6 +847,8 @@ module id_stage
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hwloop_wb_mux_sel_ex_o <= 1'b0;
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hwloop_cnt_o <= 32'b0;
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jump_in_ex <= 1'b0;
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eoc_ex_o <= 1'b0;
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`ifdef TCDM_ADDR_PRECAL
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@ -914,6 +922,8 @@ module id_stage
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hwloop_wb_mux_sel_ex_o <= hwloop_wb_mux_sel;
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hwloop_cnt_o <= hwloop_cnt;
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jump_in_ex <= jump_in_id_o;
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eoc_ex_o <= eoc;
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`ifdef TCDM_ADDR_PRECAL
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@ -178,6 +178,10 @@ module if_stage
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begin : ENABLED_PIPE
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current_pc_if_o <= next_pc;
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end
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else if ( jump_in_ex_i == 2'b01 )
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begin
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current_pc_if_o <= next_pc;
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end
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end
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end
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@ -343,10 +343,12 @@ endfunction // prettyPrintInstruction
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`define OP_C_JT 1'b1
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// operand b immediate selection
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`define IMM_I 2'b00
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`define IMM_S 2'b01
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`define IMM_U 2'b10
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`define IMM_HEX4 2'b11
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`define IMM_I 3'b000
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`define IMM_S 3'b001
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`define IMM_U 3'b010
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`define IMM_HEX4 3'b011
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`define IMM_CID 3'b100 // core id
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`define IMM_CLID 3'b100 // cluster id
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/* not used:
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`define IMM_SB 3'b011
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`define IMM_UJ 3'b101
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@ -343,11 +343,13 @@ module riscv_core
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.clk ( clk ),
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.rst_n ( rst_n ),
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.core_id_i ( core_id_i ), // TODO: Temporary hack
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// Processor Enable
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.fetch_enable_i ( fetch_enable_i ),
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.jump_in_id_o ( jump_in_id ),
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.jump_in_ex_i ( jump_in_ex ),
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.jump_in_ex_o ( jump_in_ex ),
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.core_busy_o ( core_busy_o ),
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@ -565,7 +567,7 @@ module riscv_core
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// To IF: Jump and branch target and decision
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.jump_target_o ( jump_target ),
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.jump_in_ex_o ( jump_in_ex ),
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//.jump_in_ex_o ( jump_in_ex ),
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.branch_decision_o ( branch_decision ),
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// To ID stage: Forwarding signals
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