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Make sure that core_busy signal knows about the new data event load

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This commit is contained in:
Andreas Traber 2016-03-02 15:33:46 +01:00
parent 217adf9dc0
commit 4e587ececf
2 changed files with 10 additions and 3 deletions
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5
load_store_unit.sv
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@ -67,7 +67,8 @@ module riscv_load_store_unit
output logic lsu_ready_ex_o, // LSU ready for new data in EX stage
output logic lsu_ready_wb_o, // LSU ready for new data in WB stage
input logic ex_valid_i
input logic ex_valid_i,
output logic busy_o
);
logic [31:0] data_addr_int;
@ -463,6 +464,8 @@ module riscv_load_store_unit
// generate address from operands
assign data_addr_int = (addr_useincr_ex_i) ? (operand_a_ex_i + operand_b_ex_i) : operand_a_ex_i;
assign busy_o = (CS == WAIT_RVALID) || (CS == WAIT_RVALID_EX_STALL) || (CS == IDLE_EX_STALL) || (data_req_o == 1'b1);
//////////////////////////////////////////////////////////////////////////////
// Assertions

8
riscv_core.sv
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@ -118,6 +118,7 @@ module riscv_core
logic core_busy;
logic if_busy;
logic lsu_busy;
logic [31:0] branch_pc_ex; // PC of last executed branch
@ -240,7 +241,9 @@ module riscv_core
logic perf_ld_stall;
assign core_busy_o = if_busy || core_busy;
// if we are sleeping on a barrier let's just wait on the instruction
// interface to finish loading instructions
assign core_busy_o = (data_load_event_ex && data_req_o) ? if_busy : (if_busy || core_busy || lsu_busy);
//////////////////////////////////////////////////
@ -590,7 +593,8 @@ module riscv_core
.lsu_ready_ex_o ( lsu_ready_ex ),
.lsu_ready_wb_o ( lsu_ready_wb ),
.ex_valid_i ( ex_valid )
.ex_valid_i ( ex_valid ),
.busy_o ( lsu_busy )
);
assign wb_valid = lsu_ready_wb;