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https://github.com/openhwgroup/cve2.git
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Cosmetic changes in hwloop controller, ID and includes
This commit is contained in:
Sven Stucki
parent
6cdfde93c7
commit
5a821e643b
3 changed files with 95 additions and 92 deletions
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@ -10,7 +10,7 @@
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// Create Date: 08/08/2014 //
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// Design Name: hwloop controller //
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// Module Name: hwloop_controller.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Hardware loop controller unit. This unit is responsible to //
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@ -23,8 +23,6 @@
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// //
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// //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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@ -56,7 +54,11 @@ module hwloop_controller
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// generate comparators. check for end address and the loop counter
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genvar i;
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for (i = 0; i < `HWLOOP_REGS; i++) begin
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assign pc_is_end_addr[i] = ((current_pc_i == hwloop_end_addr_i[i]) & (enable_i) & (hwloop_counter_i[i] > 32'b1)) ? 1'b1 : 1'b0;
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assign pc_is_end_addr[i] = (
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enable_i
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&& (current_pc_i == hwloop_end_addr_i[i])
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&& (hwloop_counter_i[i] > 32'b1)
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);
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end
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// output signal for ID stage
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@ -64,9 +66,10 @@ module hwloop_controller
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// select corresponding start address and decrement counter. give highest priority to register 0
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always_comb begin
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always_comb
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begin
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hwloop_targ_addr_o = 32'b0;
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hwloop_dec_cnt_o = `HWLOOP_REGS'b0;
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hwloop_dec_cnt_o = '0;
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if (pc_is_end_addr[0]) begin
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hwloop_targ_addr_o = hwloop_start_addr_i[0];
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170
id_stage.sv
170
id_stage.sv
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@ -35,91 +35,91 @@
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module id_stage
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(
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input logic clk,
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input logic rst_n,
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input logic clk,
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input logic rst_n,
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input logic fetch_enable_i,
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output logic core_busy_o,
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input logic fetch_enable_i,
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output logic core_busy_o,
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// Interface to instruction memory
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input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_ack_i,
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input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_ack_i,
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// Jumps and branches
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output logic [1:0] jump_in_id_o,
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output logic [1:0] jump_in_ex_o,
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input logic branch_decision_i,
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output logic [31:0] jump_target_o,
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output logic [1:0] jump_in_id_o,
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output logic [1:0] jump_in_ex_o,
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input logic branch_decision_i,
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output logic [31:0] jump_target_o,
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// IF and ID stage signals
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output logic compressed_instr_o,
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output logic [2:0] pc_mux_sel_o,
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output logic [1:0] exc_pc_mux_o,
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output logic force_nop_o,
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output logic compressed_instr_o,
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output logic [2:0] pc_mux_sel_o,
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output logic [1:0] exc_pc_mux_o,
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output logic force_nop_o,
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input logic [31:0] current_pc_if_i,
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input logic [31:0] current_pc_id_i,
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input logic [31:0] current_pc_if_i,
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input logic [31:0] current_pc_id_i,
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// STALLS
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output logic stall_if_o,
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output logic stall_id_o,
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output logic stall_ex_o,
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output logic stall_wb_o,
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// Stalls
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output logic stall_if_o,
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output logic stall_id_o,
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output logic stall_ex_o,
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output logic stall_wb_o,
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// To the Pipeline ID/EX
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output logic [31:0] regfile_rb_data_ex_o,
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output logic [31:0] alu_operand_a_ex_o,
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output logic [31:0] alu_operand_b_ex_o,
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output logic [31:0] alu_operand_c_ex_o,
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output logic [`ALU_OP_WIDTH-1:0] alu_operator_ex_o,
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output logic [31:0] regfile_rb_data_ex_o,
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output logic [31:0] alu_operand_a_ex_o,
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output logic [31:0] alu_operand_b_ex_o,
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output logic [31:0] alu_operand_c_ex_o,
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output logic [`ALU_OP_WIDTH-1:0] alu_operator_ex_o,
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output logic [1:0] vector_mode_ex_o,
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output logic [1:0] alu_cmp_mode_ex_o,
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output logic [1:0] alu_vec_ext_ex_o,
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output logic [1:0] vector_mode_ex_o,
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output logic [1:0] alu_cmp_mode_ex_o,
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output logic [1:0] alu_vec_ext_ex_o,
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output logic mult_en_ex_o,
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output logic [1:0] mult_sel_subword_ex_o,
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output logic [1:0] mult_signed_mode_ex_o,
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output logic mult_mac_en_ex_o,
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output logic mult_en_ex_o,
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output logic [1:0] mult_sel_subword_ex_o,
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output logic [1:0] mult_signed_mode_ex_o,
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output logic mult_mac_en_ex_o,
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output logic [4:0] regfile_waddr_ex_o,
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output logic regfile_we_ex_o,
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output logic [4:0] regfile_waddr_ex_o,
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output logic regfile_we_ex_o,
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output logic [4:0] regfile_alu_waddr_ex_o,
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output logic regfile_alu_we_ex_o,
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output logic [4:0] regfile_alu_waddr_ex_o,
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output logic regfile_alu_we_ex_o,
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output logic prepost_useincr_ex_o,
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input logic data_misaligned_i,
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output logic prepost_useincr_ex_o,
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input logic data_misaligned_i,
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output logic [2:0] hwloop_we_ex_o,
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output logic [1:0] hwloop_regid_ex_o,
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output logic hwloop_wb_mux_sel_ex_o,
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output logic [31:0] hwloop_cnt_o,
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output logic [`HWLOOP_REGS-1:0] hwloop_dec_cnt_o,
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output logic [31:0] hwloop_targ_addr_o,
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output logic [2:0] hwloop_we_ex_o,
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output logic [1:0] hwloop_regid_ex_o,
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output logic hwloop_wb_mux_sel_ex_o,
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output logic [31:0] hwloop_cnt_o,
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output logic [`HWLOOP_REGS-1:0] hwloop_dec_cnt_o,
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output logic [31:0] hwloop_targ_addr_o,
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output logic csr_access_ex_o,
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output logic [1:0] csr_op_ex_o,
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output logic csr_access_ex_o,
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output logic [1:0] csr_op_ex_o,
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// Interface to load store unit
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output logic data_we_ex_o,
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output logic [1:0] data_type_ex_o,
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output logic data_sign_ext_ex_o,
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output logic [1:0] data_reg_offset_ex_o,
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output logic data_misaligned_ex_o,
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output logic data_req_ex_o,
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input logic data_ack_i, // Grant from data memory
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input logic data_rvalid_i,
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output logic data_we_ex_o,
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output logic [1:0] data_type_ex_o,
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output logic data_sign_ext_ex_o,
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output logic [1:0] data_reg_offset_ex_o,
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output logic data_misaligned_ex_o,
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output logic data_req_ex_o,
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input logic data_ack_i, // Grant from data memory
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input logic data_rvalid_i,
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// Interrupt signals
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input logic irq_i,
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input logic irq_nm_i,
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input logic irq_enable_i,
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output logic save_pc_if_o,
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output logic save_pc_id_o,
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output logic save_sr_o,
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input logic irq_i,
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input logic irq_nm_i,
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input logic irq_enable_i,
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output logic save_pc_if_o,
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output logic save_pc_id_o,
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output logic save_sr_o,
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// from hwloop regs
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input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_i,
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@ -127,36 +127,36 @@ module id_stage
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input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_i,
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// Debug Unit Signals
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input logic dbg_flush_pipe_i,
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input logic dbg_st_en_i,
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input logic [1:0] dbg_dsr_i,
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input logic dbg_stall_i,
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output logic dbg_trap_o,
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input logic dbg_reg_mux_i,
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input logic dbg_reg_we_i,
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input logic [4:0] dbg_reg_addr_i,
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input logic [31:0] dbg_reg_wdata_i,
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output logic [31:0] dbg_reg_rdata_o,
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input logic dbg_set_npc_i,
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input logic dbg_flush_pipe_i,
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input logic dbg_st_en_i,
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input logic [1:0] dbg_dsr_i,
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input logic dbg_stall_i,
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output logic dbg_trap_o,
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input logic dbg_reg_mux_i,
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input logic dbg_reg_we_i,
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input logic [4:0] dbg_reg_addr_i,
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input logic [31:0] dbg_reg_wdata_i,
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output logic [31:0] dbg_reg_rdata_o,
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input logic dbg_set_npc_i,
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// Forward Signals
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input logic [4:0] regfile_waddr_wb_i,
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input logic regfile_we_wb_i,
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input logic [31:0] regfile_wdata_wb_i, // From wb_stage: selects data from data memory, ex_stage result and sp rdata
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input logic [4:0] regfile_waddr_wb_i,
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input logic regfile_we_wb_i,
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input logic [31:0] regfile_wdata_wb_i, // From wb_stage: selects data from data memory, ex_stage result and sp rdata
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input logic [4:0] regfile_alu_waddr_fw_i,
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input logic regfile_alu_we_fw_i,
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input logic [31:0] regfile_alu_wdata_fw_i,
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input logic [4:0] regfile_alu_waddr_fw_i,
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input logic regfile_alu_we_fw_i,
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input logic [31:0] regfile_alu_wdata_fw_i,
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`ifdef TCDM_ADDR_PRECAL
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output logic [31:0] alu_adder_o,
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output logic [31:0] alu_adder_o,
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`endif
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_branch_o, // we are executing a branch instruction (bf, bnf)
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output logic perf_jr_stall_o, // jump-register-hazard
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output logic perf_ld_stall_o // load-use-hazard
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_branch_o, // we are executing a branch instruction (bf, bnf)
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output logic perf_jr_stall_o, // jump-register-hazard
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output logic perf_ld_stall_o // load-use-hazard
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);
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@ -379,7 +379,7 @@ endfunction // prettyPrintInstruction
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`define EXC_CAUSE_ECALL {1'b0, 4'd11};
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`define EXC_CAUSE_EBREAK {1'b0, 4'd03};
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// Hardware loops addon
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// Hardware loops
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`define HWLOOP_REGS 2
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// Debug module
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