The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Sven Stucki 5a821e643b Cosmetic changes in hwloop controller, ID and includes		2015-08-31 12:34:33 +02:00
include	Cosmetic changes in hwloop controller, ID and includes	2015-08-31 12:34:33 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
compressed_decoder.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
controller.sv	Fix WFI instruction	2015-08-31 10:55:16 +02:00
cs_registers.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
debug_unit.sv	Rework pipeline flushes and exceptions	2015-08-31 10:02:55 +02:00
ex_stage.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
exc_controller.sv	Rework pipeline flushes and exceptions	2015-08-31 10:02:55 +02:00
hwloop_controller.sv	Cosmetic changes in hwloop controller, ID and includes	2015-08-31 12:34:33 +02:00
hwloop_regs.sv	Fix hwloop code indentation	2015-08-31 12:33:27 +02:00
id_stage.sv	Cosmetic changes in hwloop controller, ID and includes	2015-08-31 12:34:33 +02:00
if_stage.sv	Fix potential problem with core_busy_o, it is now also set when an	2015-08-31 10:24:39 +02:00
instr_core_interface.sv	Optimized IF intermediate step	2015-08-25 15:36:28 +02:00
load_store_unit.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
mult.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
register_file.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
riscv_core.sv	Fix potential problem with core_busy_o, it is now also set when an	2015-08-31 10:24:39 +02:00