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Move LSU related signals out of ex_stage and alu and put them inside LSU
This commit is contained in:
Andreas Traber
parent
a617bc496e
commit
5aa77089fa
4 changed files with 26 additions and 33 deletions
3
alu.sv
3
alu.sv
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@ -39,14 +39,11 @@ module alu
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input logic [1:0] cmp_mode_i,
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input logic [1:0] vec_ext_i,
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output logic [31:0] adder_lsu_o,
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output logic [31:0] result_o,
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output logic flag_o
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);
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assign adder_lsu_o = operand_a_i + operand_b_i;
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logic [31:0] operand_a_rev; // bit reversed signal of operand_a_i
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// bit reverse operand_a for left shifts
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10
ex_stage.sv
10
ex_stage.sv
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@ -52,16 +52,12 @@ module ex_stage
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input logic [1:0] mult_signed_mode_i,
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input logic mult_mac_en_i,
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output logic [31:0] data_addr_ex_o,
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// input from ID stage
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input logic stall_wb_i,
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input logic [4:0] regfile_alu_waddr_i,
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input logic regfile_alu_we_i,
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input logic prepost_useincr_i,
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// directly passed through to WB stage, not used in EX
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input logic regfile_we_i,
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input logic [4:0] regfile_waddr_i,
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@ -100,8 +96,6 @@ module ex_stage
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logic [31:0] alu_result;
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logic alu_flag;
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logic [31:0] alu_adder_lsu_int; // to LS unit
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logic [31:0] mult_result;
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@ -119,8 +113,6 @@ module ex_stage
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regfile_alu_wdata_fw_o = csr_rdata_i;
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end
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assign data_addr_ex_o = (prepost_useincr_i == 1'b1) ? alu_adder_lsu_int : alu_operand_a_i;
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// hwloop mux. selects the right data to be sent to the hwloop registers (start/end-address and counter)
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always_comb
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begin : hwloop_start_mux
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@ -159,8 +151,6 @@ module ex_stage
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.cmp_mode_i ( alu_cmp_mode_i ),
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.vec_ext_i ( alu_vec_ext_i ),
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.adder_lsu_o ( alu_adder_lsu_int ),
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.result_o ( alu_result ),
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.flag_o ( alu_flag )
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);
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@ -42,8 +42,10 @@ module load_store_unit
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output logic [31:0] data_rdata_ex_o, // requested data -> to ex stage
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input logic data_req_ex_i, // data request -> from ex stage
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input logic [31:0] data_addr_ex_i, // data address -> from ex stage
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output logic data_ack_int_o, // data ack -> to controller
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input logic [31:0] operand_a_ex_i, // operand a from RF for address -> from ex stage
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input logic [31:0] operand_b_ex_i, // operand b from RF for address -> from ex stage
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input logic addr_useincr_ex_i, // use a + b or just a for address -> from ex stage
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input logic data_misaligned_ex_i, // misaligned access in last ld/st -> from ID/EX pipeline
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output logic data_misaligned_o, // misaligned access was detected -> to controller
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@ -63,6 +65,8 @@ module load_store_unit
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input logic ex_stall_i
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);
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logic [31:0] data_addr_int;
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// registers for data_rdata alignment and sign extension
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logic [1:0] data_type_q;
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logic [1:0] rdata_offset_q;
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@ -94,21 +98,21 @@ module load_store_unit
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begin // Writing a word
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if (misaligned_st == 1'b0)
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begin // non-misaligned case
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case (data_addr_ex_i[1:0])
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case (data_addr_int[1:0])
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2'b00: data_be = 4'b1111;
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2'b01: data_be = 4'b1110;
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2'b10: data_be = 4'b1100;
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2'b11: data_be = 4'b1000;
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endcase; // case (data_addr_ex_i[1:0])
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endcase; // case (data_addr_int[1:0])
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end
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else
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begin // misaligned case
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case (data_addr_ex_i[1:0])
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case (data_addr_int[1:0])
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2'b00: data_be = 4'b0000; // this is not used, but included for completeness
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2'b01: data_be = 4'b0001;
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2'b10: data_be = 4'b0011;
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2'b11: data_be = 4'b0111;
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endcase; // case (data_addr_ex_i[1:0])
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endcase; // case (data_addr_int[1:0])
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end
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end
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@ -116,12 +120,12 @@ module load_store_unit
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begin // Writing a half word
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if (misaligned_st == 1'b0)
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begin // non-misaligned case
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case (data_addr_ex_i[1:0])
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case (data_addr_int[1:0])
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2'b00: data_be = 4'b0011;
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2'b01: data_be = 4'b0110;
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2'b10: data_be = 4'b1100;
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2'b11: data_be = 4'b1000;
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endcase; // case (data_addr_ex_i[1:0])
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endcase; // case (data_addr_int[1:0])
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end
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else
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begin // misaligned case
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@ -131,12 +135,12 @@ module load_store_unit
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2'b10,
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2'b11: begin // Writing a byte
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case (data_addr_ex_i[1:0])
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case (data_addr_int[1:0])
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2'b00: data_be = 4'b0001;
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2'b01: data_be = 4'b0010;
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2'b10: data_be = 4'b0100;
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2'b11: data_be = 4'b1000;
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endcase; // case (data_addr_ex_i[1:0])
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endcase; // case (data_addr_int[1:0])
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end
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endcase; // case (data_type_ex_i)
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end
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@ -144,7 +148,7 @@ module load_store_unit
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// prepare data to be written to the memory
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// we handle misaligned accesses, half word and byte accesses and
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// register offsets here
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assign wdata_offset = data_addr_ex_i[1:0] - data_reg_offset_ex_i[1:0];
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assign wdata_offset = data_addr_int[1:0] - data_reg_offset_ex_i[1:0];
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always_comb
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begin
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case (wdata_offset)
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@ -168,7 +172,7 @@ module load_store_unit
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else if (request_entered == 1'b1) // request entered FSM
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begin
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data_type_q <= data_type_ex_i;
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rdata_offset_q <= data_addr_ex_i[1:0];
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rdata_offset_q <= data_addr_int[1:0];
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data_sign_ext_q <= data_sign_ext_ex_i;
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end
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end
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@ -355,7 +359,7 @@ module load_store_unit
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begin
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data_req_o = 1'b0;
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data_we_o = 1'b0;
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data_addr_o = data_addr_ex_i;
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data_addr_o = data_addr_int;
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data_wdata_o = data_wdata;
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data_be_o = data_be;
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misaligned_st = data_misaligned_ex_i;
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@ -407,7 +411,7 @@ module load_store_unit
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begin
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NS = PENDING_WO_EX_STALL;
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end
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else
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else
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begin
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NS = WAIT_GNT;
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end
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@ -490,16 +494,20 @@ module load_store_unit
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case (data_type_ex_i)
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2'b00: // word
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begin
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if(data_addr_ex_i[1:0] != 2'b00)
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if(data_addr_int[1:0] != 2'b00)
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data_misaligned_o = 1'b1;
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end
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2'b01: // half word
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begin
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if(data_addr_ex_i[1:0] == 2'b11)
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if(data_addr_int[1:0] == 2'b11)
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data_misaligned_o = 1'b1;
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end
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endcase // case (data_type_ex_i)
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end
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end
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// generate address from operands
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assign data_addr_int = (addr_useincr_ex_i) ? (operand_a_ex_i + operand_b_ex_i) : operand_a_ex_i;
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endmodule
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@ -462,8 +462,6 @@ module riscv_core
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// input from ID stage
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.stall_wb_i ( stall_wb ),
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.prepost_useincr_i ( useincr_addr_ex ),
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// From ID Stage: Regfile control signals
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.regfile_waddr_i ( regfile_waddr_ex ),
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.regfile_we_i ( regfile_we_ex ),
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@ -484,8 +482,6 @@ module riscv_core
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.regfile_we_wb_o ( regfile_we_wb ),
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.regfile_rb_data_wb_o ( regfile_rb_data_wb ),
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.data_addr_ex_o ( data_addr_ex ),
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// To hwloop regs
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.hwloop_start_data_o ( hwlp_start_data_ex ),
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.hwloop_end_data_o ( hwlp_end_data_ex ),
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@ -524,8 +520,10 @@ module riscv_core
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.data_rdata_ex_o ( regfile_wdata ),
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.data_req_ex_i ( data_req_ex ),
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.data_addr_ex_i ( data_addr_ex ),
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.data_ack_int_o ( data_ack_int ), // ack used in controller to stall
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.operand_a_ex_i ( alu_operand_a_ex ),
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.operand_b_ex_i ( alu_operand_b_ex ),
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.addr_useincr_ex_i ( useincr_addr_ex ),
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.data_misaligned_ex_i ( data_misaligned_ex ), // from ID/EX pipeline
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.data_misaligned_o ( data_misaligned ),
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