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Fix compile errors from last commit, fix synthesis warnigns and remove

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unused signals
This commit is contained in:
Andreas Traber 2015-09-02 08:38:25 +02:00
parent 3a4ddb2af3
commit a617bc496e
5 changed files with 12 additions and 21 deletions
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11
alu.sv
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@ -41,8 +41,6 @@ module alu
output logic [31:0] adder_lsu_o,
output logic [31:0] result_o,
output logic overflow_o,
output logic carry_o,
output logic flag_o
);
@ -538,18 +536,11 @@ module alu
shift_left = 1'b0;
shift_amt = operand_b_i;
result_o = 'x;
carry_o = 1'b0;
overflow_o = 1'b0;
flag_o = 1'b0;
unique case (operator_i)
// Standard Operations
`ALU_ADD, `ALU_SUB:
begin // Addition defined above
result_o = adder_result[31:0];
carry_o = carry_out[3];
overflow_o = (adder_op_a[31] ^ adder_result[31]) & (adder_op_b[31] ^ adder_result[31]); // ++ => - and -- => +
end
`ALU_ADD, `ALU_SUB: result_o = adder_result;
`ALU_AVG, `ALU_AVGU: result_o = result_avg;
`ALU_AND: result_o = operand_a_i & operand_b_i;
`ALU_OR: result_o = operand_a_i | operand_b_i;

1
cs_registers.sv
View file

@ -102,6 +102,7 @@ module cs_registers
// CSR update logic
logic [31:0] csr_wdata_int;
logic [31:0] csr_rdata_int;
logic csr_we_int;
// Interrupt control signals

3
if_stage.sv
View file

@ -193,9 +193,10 @@ module if_stage
.rst_n ( rst_n ),
.req_i ( fetch_req ),
.valid_o ( fetch_valid ),
.addr_i ( fetch_addr_n ),
.valid_o ( fetch_valid ),
.rdata_o ( fetch_rdata ),
.last_addr_o ( fetch_addr_Q ),
.instr_req_o ( instr_req_o ),
.instr_addr_o ( instr_addr_o ),

7
load_store_unit.sv
View file

@ -37,10 +37,10 @@ module load_store_unit
input logic data_we_ex_i, // write enable -> from ex stage
input logic [1:0] data_type_ex_i, // Data type word, halfword, byte -> from ex stage
input logic [31:0] data_wdata_ex_i, // data to write to memory -> from ex stage
input logic data_sign_ext_ex_i, // sign extension -> from ex stage
input logic [1:0] data_reg_offset_ex_i, // offset inside register for stores -> from ex stage
input logic data_sign_ext_ex_i, // sign extension -> from ex stage
output logic [31:0] data_rdata_ex_o, // requested data -> to ex stage
output logic [31:0] lsu_data_reg_o, // requested data registered -> to id stage
input logic data_req_ex_i, // data request -> from ex stage
input logic [31:0] data_addr_ex_i, // data address -> from ex stage
output logic data_ack_int_o, // data ack -> to controller
@ -349,9 +349,6 @@ module load_store_unit
// output to register file
assign data_rdata_ex_o = (latch_rdata == 1'b1) ? data_rdata_ext : rdata_q;
// registered result of data request
assign lsu_data_reg_o = rdata_q;
// FSM
always_comb

11
riscv_core.sv
View file

@ -520,8 +520,8 @@ module riscv_core
.data_type_ex_i ( data_type_ex ),
.data_wdata_ex_i ( regfile_rb_data_ex ),
.data_reg_offset_ex_i ( data_reg_offset_ex ),
.data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension
.data_rdata_ex_o ( regfile_wdata ),
.data_req_ex_i ( data_req_ex ),
.data_addr_ex_i ( data_addr_ex ),
@ -531,13 +531,14 @@ module riscv_core
.data_misaligned_o ( data_misaligned ),
//output to data memory
.data_req_o ( data_req_o ),
.data_addr_o ( data_addr_o ),
.data_we_o ( data_we_o ),
.data_be_o ( data_be_o ),
.data_wdata_o ( data_wdata_o ),
.data_rdata_i ( data_rdata_i ),
.data_rvalid_i ( data_r_valid_i ),
.data_addr_o ( data_addr_o ),
.data_we_o ( data_we_o ),
.data_req_o ( data_req_o ),
.data_gnt_i ( data_gnt_i ),
.ex_stall_i ( stall_ex )
@ -578,7 +579,7 @@ module riscv_core
.save_pc_if_i ( save_pc_if ),
.save_pc_id_i ( save_pc_id ),
.irq_enable_o ( irq_enable )
.irq_enable_o ( irq_enable ),
.epcr_o ( epcr ),
// performance counter related signals