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Vendor in hw/dv/{data,tools} from OpenTitan

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This gets the rest of the support code needed for dvsim (which we
currently duplicate). The patch:

  - adds the relevant directories to the vendoring file
  - adds a patch to rewrite some OpenTitan-specific bits
  - adds a "common_project_cfg.hjson"
  - re-runs the vendoring tool

This patch won't yet change how DV code runs; we also need to redirect
a couple of paths and delete dv/uvm/data for that. This will happen in
the next patch.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This commit is contained in:
Rupert Swarbrick 2020-11-26 17:01:29 +00:00 • committed by Rupert Swarbrick
parent 690f8af65e
commit 623402cf6f
50 changed files with 2651 additions and 0 deletions
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18
dv/uvm/common_project_cfg.hjson Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
project: ibex
// These keys are expected by dvsim.py, so we have to set them to something.
doc_server: bogus.doc.server
results_server: bogus.results.server
// Default directory structure for the output
scratch_base_path: "{scratch_root}/{dut}.{flow}.{tool}"
scratch_path: "{scratch_base_path}/{branch}"
tool_srcs_dir: "{scratch_path}/{tool}"
// The current design level
design_level: "ip"
}

9
vendor/lowrisc_ip.vendor.hjson vendored
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@ -11,10 +11,19 @@
}
mapping: [
// We have to apply a patch to the vendored files from hw/dv/data,
// because they contain an OpenTitan specific path.
{
from: "hw/dv/data",
to: "dv/data",
patch_dir: "dv_data"
},
{from: "hw/dv/sv/common_ifs", to: "dv/sv/common_ifs"},
{from: "hw/dv/sv/csr_utils", to: "dv/sv/csr_utils"},
{from: "hw/dv/sv/dv_base_reg", to: "dv/sv/dv_base_reg"},
{from: "hw/dv/sv/mem_model", to: "dv/sv/mem_model"},
{from: "hw/dv/tools", to: "dv/tools"},
{from: "hw/dv/verilator", to: "dv/verilator"},
// We apply a patch to fix the bus_params_pkg core file name when

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vendor/lowrisc_ip/dv/data/common_modes.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
// Sim modes are collection of build_opts and run_opts
// These are only set on the command line
// These are different from the build modes in the sense that these collection of
// options are appended to actual build_modes
build_modes: [
{
name: waves
is_sim_mode: 1
en_build_modes: ["{tool}_waves"]
}
{
name: cov
is_sim_mode: 1
en_build_modes: ["{tool}_cov"]
}
{
name: profile
is_sim_mode: 1
en_build_modes: ["{tool}_profile"]
}
{
name: xprop
is_sim_mode: 1
en_build_modes: ["{tool}_xprop"]
}
{
name: loopdetect
is_sim_mode: 1
en_build_modes: ["{tool}_loopdetect"]
}
]
run_modes: [
{
name: uvm_trace
run_opts: ["+UVM_PHASE_TRACE", "+UVM_CONFIG_DB_TRACE", "+UVM_OBJECTION_TRACE"]
}
]
}

153
vendor/lowrisc_ip/dv/data/common_sim_cfg.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
// Where to find DV code
dv_root: "{proj_root}/vendor/lowrisc_ip/dv"
flow: sim
flow_makefile: "{dv_root}/data/sim.mk"
import_cfgs: ["{proj_root}/dv/uvm/common_project_cfg.hjson",
"{dv_root}/data/common_modes.hjson",
"{dv_root}/data/fusesoc.hjson",
"{dv_root}/data/{tool}/{tool}.hjson"]
// Default directory structure for the output
build_dir: "{scratch_path}/{build_mode}"
run_dir_name: "{index}.{test}"
run_dir: "{scratch_path}/{run_dir_name}/out"
sw_build_dir: "{scratch_path}/sw"
sw_root_dir: "{proj_root}/sw"
// pass and fail patterns
build_pass_patterns: []
build_fail_patterns: ["^ERROR:.*$"] // fusesoc build error
run_pass_patterns: ["^TEST PASSED (UVM_)?CHECKS$"]
run_fail_patterns: ["^UVM_ERROR\\s[^:].*$",
"^UVM_FATAL\\s[^:].*$",
"^UVM_WARNING\\s[^:].*$",
"^Assert failed: ",
"^\\s*Offending '.*'",
"^TEST FAILED (UVM_)?CHECKS$"]
// Default TileLink widths
tl_aw: 32
tl_dw: 32
tl_dbw: 4
// Default UVM verbosity settings
n: UVM_NONE
l: UVM_LOW
m: UVM_MEDIUM
h: UVM_HIGH
d: UVM_DEBUG
// Path to the dut instance (this is used in a couple of places such as coverage cfg
// file, xprop cfg file etc. If this is different for your block, then override it with
// the 'overrides' directive.
dut_instance: "{tb}.dut"
// Top level simulation entities.
sim_tops: ["-top {tb}"]
// Default build and run opts
build_opts: [// List multiple tops for the simulation
"{sim_tops}",
// Standard UVM defines
"+define+UVM",
"+define+UVM_NO_DEPRECATED",
"+define+UVM_REGEX_NO_DPI",
"+define+UVM_REG_ADDR_WIDTH={tl_aw}",
"+define+UVM_REG_DATA_WIDTH={tl_dw}",
"+define+UVM_REG_BYTENABLE_WIDTH={tl_dbw}"]
run_opts: ["+UVM_NO_RELNOTES",
"+UVM_VERBOSITY={verbosity}"]
// Default list of things to export to shell
exports: [
TOOL_SRCS_DIR: {tool_srcs_dir}
EN_WAVES: {waves}
DUMP_FMT: {dump_fmt}
DUT_TOP: {dut}
TB_TOP: {tb}
dut_instance: {dut_instance}
]
// Build modes are collection of build_opts and run_opts
// A test can enable a specific build mode by setting 'use_build_mode' key
build_modes: [
{
name: foo
build_opts: ["+define+bx",
"+define+by",
"+define+bz"]
run_opts: ["+rx=1",
"+ry=2",
"+rz=3"]
}
{
name: bar
build_opts: ["+define+bbaru1",
"+define+bbaru2",
"+define+bbaru3"]
run_opts: ["+rbar1u=1",
"+rbar2u=2",
"+rbar3u=3"]
}
{
name: cover_reg_top
}
]
// Regressions are tests that can be grouped together and run in one shot
// By default, two regressions are made available - "all" and "nightly". Both
// run all available tests for the DUT. "nightly" enables coverage as well.
// The 'tests' key is set to an empty list, which indicates "run everything".
// Test sets can enable sim modes, which are a set of build_opts and run_opts
// that are grouped together. These are appended to the build modes used by the
// tests.
regressions: [
{
name: sanity
tests: []
reseed: 1
}
{
name: all
}
{
name: all_once
reseed: 1
}
{
name: nightly
en_sim_modes: ["cov"]
}
]
// Add waves.tcl to the set of sources to be copied over to
// {tool_srcs_dir}. This can be sourced by the tool-specific TCL
// script to set up wave dumping.
tool_srcs: ["{dv_root}/tools/waves.tcl"],
// Project defaults for VCS
vcs_cov_cfg_file: "{{build_mode}_vcs_cov_cfg_file}"
vcs_cov_excl_files: ["{tool_srcs_dir}/common_cov_excl.el"]
// Build-specific coverage cfg files for VCS.
default_vcs_cov_cfg_file: "-cm_hier {tool_srcs_dir}/cover.cfg"
cover_reg_top_vcs_cov_cfg_file: "-cm_hier {tool_srcs_dir}/cover_reg_top.cfg"
// Project defaults for Xcelium
// xcelium_cov_cfg_file: "{{build_mode}_xcelium_cov_cfg_file}"
// xcelium_cov_refine_files: ["{tool_srcs_dir}/common_cov.vRefine"]
// Build-specific coverage cfg files for Xcelium.
// default_xcelium_cov_cfg_file: "-covfile {tool_srcs_dir}/cover.ccf"
// cover_reg_top_xcelium_cov_cfg_file: "-covfile {tool_srcs_dir}/cover_reg_top.ccf"
}

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vendor/lowrisc_ip/dv/data/dsim/dsim.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_cmd: "{job_prefix} dsim"
run_cmd: "{job_prefix} dsim"
build_opts: [
"-work {build_dir}/dsim_out",
"-genimage image",
"-sv",
// Set parallel compilation jobs limit
"-j 12",
// UVM
"+incdir+{UVM_HOME}/src",
"{UVM_HOME}/src/uvm_pkg.sv",
// Add dpi/vpi include path.
"-c-opts -I{DSIM_HOME}/include",
"-timescale 1ns/1ps",
"-f {sv_flist}",
"+incdir+{build_dir}",
// Suppress following DSim errors and warnings:
// EnumMustBePositive - UVM 1.2 violates this
"-suppress EnumMustBePositive"
]
run_opts: [
"-work {build_dir}/dsim_out",
"-image image",
// UVM DPI
"-sv_lib {DSIM_HOME}/lib/libuvm_dpi.so",
"-sv_seed {seed}",
// tell DSim to write line-buffered std output (lines will be written in proper order)
"-linebuf",
"+UVM_TESTNAME={uvm_test}",
"+UVM_TEST_SEQ={uvm_test_seq}"]
// Indicate the tool specific helper sources - these are copied over to the
// {tool_srcs_dir} before running the simulation.
// TODO, there is no dsim tool file, point to vcs for now to avoid error from script
tool_srcs: ["{dv_root}/tools/vcs/*"]
// TODO: refactor coverage configuration for DSim.
// COVERAGE related.
cov_db_dir: "{scratch_path}/coverage/{build_mode}.vdb"
// Individual test specific coverage data - this will be deleted if the test fails
// so that coverage from failing tests is not included in the final report.
cov_db_test_dir_name: "{run_dir_name}.{seed}"
cov_db_test_dir: "{cov_db_dir}/snps/coverage/db/testdata/{cov_db_test_dir_name}"
// Merging coverage.
// "cov_db_dirs" is a special variable that appends all build directories in use.
// It is constructed by the tool itself.
cov_merge_dir: "{scratch_base_path}/cov_merge"
cov_merge_db_dir: "{cov_merge_dir}/merged.vdb"
cov_merge_cmd: "{job_prefix} urg"
cov_merge_opts: [
]
// Generate coverage reports in text as well as html.
cov_report_dir: "{scratch_base_path}/cov_report"
cov_report_cmd: "{job_prefix} urg"
cov_report_opts: [
]
cov_report_txt: "{cov_report_dir}/dashboard.txt"
cov_report_page: "dashboard.html"
// Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
// GUI for visual analysis.
cov_analyze_dir: "{scratch_base_path}/cov_analyze"
cov_analyze_cmd: "{job_prefix} verdi"
cov_analyze_opts: ["-cov",
"-covdir {cov_merge_db_dir}",
"-line nocasedef"
"-elfile {vcs_cov_excl_files}"]
// Vars that need to exported to the env.
exports: [
]
// Defaults for DSim
// TODO: there is currently no equivalent of "all" coverage metrics in DSim
cov_metrics: ""
// pass and fail patterns
build_fail_patterns: ["^Error-.*$"]
run_fail_patterns: ["^Error-.*$"] // Null pointer error
// waveform
wave_type: "vcd"
wave_file: "dsim_wave.{wave_type}"
probe_file: "dsim.probe"
build_modes: [
{
name: dsim_waves
is_sim_mode: 1
build_opts: [
"+acc+b"
]
run_opts: [
"-waves {wave_file}",
// dsim.probe is currently undefined
//"-wave-scope-specs {probe_file}",
// Dump unpacked structs and arrays.
"-dump-agg"
]
}
// TODO: support coverage mode
// Note: no specific build or run options are required for dsim to produce functional
// coverage. Code coverage support is evolving.
{
name: dsim_cov
is_sim_mode: 1
build_opts: [// Enable the required cov metrics
]
run_opts: [// Enable the required cov metrics
]
}
// TODO: support xprop mode
{
name: dsim_xprop
is_sim_mode: 1
}
{
name: dsim_profile
is_sim_mode: 1
run_opts: ["-profile"]
}
{
// TODO: Add build and run options to enable zero delay loop detection.
name: dsim_loopdetect
is_sim_mode: 1
build_opts: []
run_opts: []
}
]
}

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vendor/lowrisc_ip/dv/data/fusesoc.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
sv_flist_gen_cmd: fusesoc
fusesoc_core_: "{eval_cmd} echo \"{fusesoc_core}\" | tr ':' '_'"
sv_flist_gen_opts: ["{fusesoc_cores_root_dirs}",
"run",
"--flag=fileset_{design_level}",
"--target=sim",
"--build-root={build_dir}",
"--setup {fusesoc_core}"]
fusesoc_cores_root_dirs: ["--cores-root {proj_root}"]
sv_flist_gen_dir: "{build_dir}/sim-vcs"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
}

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vendor/lowrisc_ip/dv/data/riviera/riviera.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_cmd: "vlib work && {job_prefix} vlog"
run_cmd: "{job_prefix} vsim"
// Indicate the tool specific helper sources - these are copied over to the
// {tool_srcs_dir} before running the simulation.
tool_srcs: ["{proj_root}/dv/uvm/data/riviera/*"]
build_opts: ["-sv",
"-timescale 1ns/1ps",
"-uvmver 1.2",
"-f {sv_flist}"]
run_opts: ["-sv_seed={seed}",
"-c",
"{tb}",
"-lib {sv_flist_gen_dir}/work",
"+UVM_TESTNAME={uvm_test}",
"+UVM_TEST_SEQ={uvm_test_seq}",
"-do {tool_srcs_dir}/riviera_run.do"]
// Coverage related.
// TODO: These options have to be filled in.
cov_db_dir: ""
// Individual test specific coverage data - this will be deleted if the test fails
// so that coverage from failiing tests is not included in the final report.
cov_db_test_dir_name: "{run_dir_name}.{seed}"
cov_db_test_dir: ""
// Merging coverage.
// "cov_db_dirs" is a special variable that appends all build directories in use.
// It is constructed by the tool itself.
cov_merge_dir: "{scratch_base_path}/cov_merge"
cov_merge_db_dir: ""
cov_merge_cmd: ""
cov_merge_opts: []
// Generate covreage reports in text as well as html.
cov_report_dir: "{scratch_base_path}/cov_report"
cov_report_cmd: ""
cov_report_opts: []
cov_report_dashboard: ""
// Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
// GUI for visual analysis.
cov_analyze_dir: "{scratch_base_path}/cov_analyze"
cov_analyze_cmd: ""
cov_analyze_opts: []
// pass and fail patterns
build_fail_patterns: ["\\*E.*$"]
run_fail_patterns: ["\\*E.*$"] // Null pointer error
build_modes: [
{
name: riviera_waves
is_sim_mode: 1
}
// TODO support coverage for riviera
{
name: riviera_cov
is_sim_mode: 1
build_opts: []
run_opts: []
}
// TODO support profiling for riviera
{
name: riviera_profile
is_sim_mode: 1
build_opts: []
run_opts: []
}
{
name: riviera_xprop
is_sim_mode: 1
build_opts: []
}
]
}

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vendor/lowrisc_ip/dv/data/riviera/riviera_run.do vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Do not print "KERNEL: " in front of messages to ensure user-printed messages
# match the filter expected by the DV environment.
unset messageprefix
pref.setvalue application/console/general/show-identifier-in-messages false
run -all
endsim
pref.setvalue application/console/general/show-identifier-in-messages true

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vendor/lowrisc_ip/dv/data/sim.mk vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
.DEFAULT_GOAL := all
LOCK_TOOL_SRCS_DIR ?= flock --timeout 3600 ${tool_srcs_dir} --command
LOCK_SW_BUILD ?= flock --timeout 3600 ${sw_build_dir} --command
all: build run
###############################
## sim build and run targets ##
###############################
build: compile_result
prep_tool_srcs:
@echo "[make]: prep_tool_srcs"
mkdir -p ${tool_srcs_dir}
${LOCK_TOOL_SRCS_DIR} "cp -Ru ${tool_srcs} ${tool_srcs_dir}/."
pre_compile:
@echo "[make]: pre_compile"
mkdir -p ${build_dir}
gen_sv_flist: pre_compile prep_tool_srcs
@echo "[make]: gen_sv_flist"
cd ${build_dir} && ${sv_flist_gen_cmd} ${sv_flist_gen_opts}
compile: gen_sv_flist
@echo "[make]: compile"
cd ${sv_flist_gen_dir} && ${build_cmd} ${build_opts}
post_compile: compile
@echo "[make]: post_compile"
compile_result: post_compile
@echo "[make]: compile_result"
run: run_result
pre_run:
@echo "[make]: pre_run"
mkdir -p ${run_dir}
ifneq (${sw_test},)
mkdir -p ${sw_build_dir}
endif
sw_build: pre_run
@echo "[make]: sw_build"
ifneq (${sw_test},)
# Initialize meson build system.
${LOCK_SW_BUILD} "cd ${proj_root} && \
BUILD_ROOT=${sw_build_dir} ${proj_root}/meson_init.sh"
# Compile boot rom code and generate the image.
${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \
sw/device/boot_rom/boot_rom_export_${sw_build_device}"
# Extract the boot rom logs.
${proj_root}/util/device_sw_utils/extract_sw_logs.py \
-e "${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.elf" \
-f .logs.fields -r .rodata .chip_info \
-n "rom" -o "${run_dir}"
# Copy over the boot rom image to the run_dir.
cp ${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.32.vmem \
${run_dir}/rom.32.vmem
ifeq (${sw_test_is_prebuilt},1)
# Copy over the sw test image and related sources to the run_dir.
cp ${proj_root}/${sw_test}.64.vmem ${run_dir}/sw.64.vmem
# Optionally, assume that ${sw_test}_logs.txt exists and copy over to the run_dir.
# Ignore copy error if it actually doesn't exist. Likewise for ${sw_test}_rodata.txt.
-cp ${proj_root}/${sw_test}_logs.txt ${run_dir}/sw_logs.txt
-cp ${proj_root}/${sw_test}_rodata.txt ${run_dir}/sw_rodata.txt
else
# Compile the sw test code and generate the image.
${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \
${sw_test}_export_${sw_build_device}"
# Extract the sw test logs.
${proj_root}/util/device_sw_utils/extract_sw_logs.py \
-e "${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.elf" \
-f .logs.fields -r .rodata \
-n "sw" -o "${run_dir}"
# Copy over the sw test image to the run_dir.
cp ${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.64.vmem \
${run_dir}/sw.64.vmem
endif
endif
simulate: sw_build
@echo "[make]: simulate"
cd ${run_dir} && ${run_cmd} ${run_opts}
post_run: simulate
@echo "[make]: post_run"
run_result: post_run
@echo "[make]: run_result"
#######################
## Load waves target ##
#######################
debug_waves:
${debug_waves_cmd} ${debug_waves_opts}
############################
## coverage rated targets ##
############################
# Merge coverage if there are multiple builds.
cov_merge:
@echo "[make]: cov_merge"
${cov_merge_cmd} ${cov_merge_opts}
# Open coverage tool to review and create report or exclusion file.
cov_analyze: prep_tool_srcs
@echo "[make]: cov_analyze"
${cov_analyze_cmd} ${cov_analyze_opts}
# Generate coverage reports.
cov_report:
@echo "[make]: cov_report"
${cov_report_cmd} ${cov_report_opts}
.PHONY: build \
run \
reg \
pre_compile \
compile \
post_compile \
compile_result \
pre_run \
simulate \
post_run \
run_result

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vendor/lowrisc_ip/dv/data/tests/csr_tests.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_modes: [
{
name: cover_reg_top
}
]
run_modes: [
{
name: csr_tests_mode
uvm_test_seq: "{name}_common_vseq"
run_opts: ["+en_scb=0"]
}
]
tests: [
{
name: "{name}_csr_hw_reset"
build_mode: "cover_reg_top"
run_opts: ["+csr_hw_reset"]
en_run_modes: ["csr_tests_mode"]
}
{
name: "{name}_csr_rw"
build_mode: "cover_reg_top"
run_opts: ["+csr_rw"]
en_run_modes: ["csr_tests_mode"]
}
{
name: "{name}_csr_bit_bash"
build_mode: "cover_reg_top"
run_opts: ["+csr_bit_bash"]
en_run_modes: ["csr_tests_mode"]
}
{
name: "{name}_csr_aliasing"
build_mode: "cover_reg_top"
run_opts: ["+csr_aliasing"]
en_run_modes: ["csr_tests_mode"]
}
{
name: "{name}_same_csr_outstanding"
build_mode: "cover_reg_top"
run_opts: ["+run_same_csr_outstanding"]
en_run_modes: ["csr_tests_mode"]
}
{
name: "{name}_csr_mem_rw_with_rand_reset"
build_mode: "cover_reg_top"
run_opts: ["+run_csr_mem_rw_with_rand_reset", "+test_timeout_ns=10000000000"]
en_run_modes: ["csr_tests_mode"]
}
]
regressions: [
{
name: sanity
tests: ["{name}_csr_hw_reset", "{name}_csr_rw"]
}
{
name: sw_access
tests: ["{name}_csr_hw_reset",
"{name}_csr_rw",
"{name}_csr_bit_bash",
"{name}_csr_aliasing",
"{name}_same_csr_outstanding"]
}
]
}

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vendor/lowrisc_ip/dv/data/tests/intr_test.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_modes: [
{
name: cover_reg_top
}
]
tests: [
{
name: "{name}_intr_test"
build_mode: "cover_reg_top"
uvm_test_seq: "{name}_common_vseq"
run_opts: ["+run_intr_test"]
reseed: 50
}
]
}

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vendor/lowrisc_ip/dv/data/tests/mem_tests.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_modes: [
{
name: cover_reg_top
}
]
run_modes: [
{
name: mem_tests_mode
uvm_test_seq: "{name}_common_vseq"
run_opts: ["+en_scb=0"]
}
]
tests: [
{
name: "{name}_mem_walk"
build_mode: "cover_reg_top"
en_run_modes: ["mem_tests_mode"]
run_opts: ["+csr_mem_walk"]
}
{
name: "{name}_mem_partial_access"
build_mode: "cover_reg_top"
en_run_modes: ["mem_tests_mode"]
run_opts: ["+run_mem_partial_access"]
}
]
regressions: [
{
name: sw_access
tests: ["{name}_mem_walk",
"{name}_mem_partial_access"]
}
]
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_modes: [
{
name: cover_reg_top
}
]
run_modes: [
{
name: csr_tests_mode
uvm_test_seq: "{name}_common_vseq"
run_opts: ["+en_scb=0"]
}
]
tests: [
{
// this hjson should be imported by all IPs containing shadowed CSRs
name: "{name}_shadow_reg_errors"
build_mode: "cover_reg_top"
run_opts: ["+run_shadow_reg_errors"]
en_run_modes: ["csr_tests_mode"]
}
]
regressions: [
{
name: sw_access
tests: ["{name}_shadow_reg_errors"]
}
]
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
tests: [
{
name: "{name}_stress_all"
uvm_test_seq: "{name}_stress_all_vseq"
// 10ms
run_opts: ["+test_timeout_ns=10000000000"]
}
{
name: "{name}_stress_all_with_rand_reset"
uvm_test_seq: "{name}_common_vseq"
run_opts: ["+run_stress_all_with_rand_reset",
// 10ms
"+test_timeout_ns=10000000000",
"+stress_seq={name}_stress_all_vseq"]
}
]
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_modes: [
{
name: cover_reg_top
}
]
tests: [
{
name: "{name}_tl_errors"
build_mode: "cover_reg_top"
uvm_test_seq: "{name}_common_vseq"
run_opts: ["+run_tl_errors"]
reseed: 20
}
]
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_cmd: "{job_prefix} vcs"
build_ex: "{build_dir}/simv"
run_cmd: "{job_prefix} {build_ex}"
// Indicate the tool specific helper sources - these are copied over to the
// {tool_srcs_dir} before running the simulation.
tool_srcs: ["{dv_root}/tools/vcs/*"]
build_opts: ["-sverilog -full64 -licqueue -kdb -ntb_opts uvm-1.2",
"-timescale=1ns/1ps",
"-Mdir={build_ex}.csrc",
"-o {build_ex}",
"-f {sv_flist}",
"+incdir+{build_dir}",
// Turn on warnings for non-void functions called with return values ignored
"+warn=SV-NFIVC",
"+warn=noUII-L",
// Below option required for $error/$fatal system calls
"-assert svaext",
// Force unique and priority to evaluate compliance checking only on the stable
// and final value of the selection input at the end of a simulation timestep.
// See https://github.com/lowRISC/ibex/issues/845.
"-xlrm uniq_prior_final",
// Force DPI-C compilation in C99 mode
"-CFLAGS \"--std=c99\"",
// Without this magic LDFLAGS argument below, we get compile time errors with
// VCS on Google Linux machines that look like this:
// .../libvcsnew.so: undefined reference to `snpsReallocFunc'
// .../libvcsnew.so: undefined reference to `snpsCheckStrdupFunc'
// .../libvcsnew.so: undefined reference to `snpsGetMemBytes'
"-LDFLAGS \"-Wl,--no-as-needed\"",
// This option enables the following: (needed for uvm_hdl_*)
// - Read capability on registers, variables, and nets
// - Write (deposit) capability on registers and variables
// - Force capability on registers, variables, and nets
"-debug_access+f"]
run_opts: ["-licqueue",
"-ucli -do {tool_srcs_dir}/vcs.tcl",
"+ntb_random_seed={seed}",
// Disable the display of the SystemVerilog assert and cover statement summary
// at the end of simulation. This summary is list of assertions that started but
// did not finish because the simulation terminated, or assertions that did not
// fire at all. The latter is analyzed anyway in the collected coverage. Neither
// of these is useful in regular simulations.
"-assert nopostproc",
"+UVM_TESTNAME={uvm_test}",
"+UVM_TEST_SEQ={uvm_test_seq}"]
// Coverage related.
cov_db_dir: "{scratch_path}/coverage/{build_mode}.vdb"
// Individual test specific coverage data - this will be deleted if the test fails
// so that coverage from failiing tests is not included in the final report.
cov_db_test_dir_name: "{run_dir_name}.{seed}"
cov_db_test_dir: "{cov_db_dir}/snps/coverage/db/testdata/{cov_db_test_dir_name}"
// Merging coverage.
// "cov_db_dirs" is a special variable that appends all build directories in use.
// It is constructed by the tool itself.
cov_merge_dir: "{scratch_base_path}/cov_merge"
cov_merge_db_dir: "{cov_merge_dir}/merged.vdb"
cov_merge_cmd: "{job_prefix} urg"
cov_merge_opts: ["-full64",
"+urg+lic+wait",
"-nocheck",
"-noreport",
"-flex_merge drop",
"-group merge_across_scopes",
"-parallel",
"-parallel_split 20",
// Use cov_db_dirs var for dir args; append -dir in front of each
'''{eval_cmd} dirs=`echo {cov_db_dirs}`; dir_args=; \
for d in $dirs; do dir_args="$dir_args -dir $d"; done; \
echo $dir_args
''',
"-dbname {cov_merge_db_dir}"]
// Generate coverage reports in text as well as html.
cov_report_dir: "{scratch_base_path}/cov_report"
cov_report_cmd: "{job_prefix} urg"
cov_report_opts: ["-full64",
"+urg+lic+wait",
"-dir {cov_merge_db_dir}",
"-group instcov_for_score",
"-line nocasedef",
"-format both",
"-elfile {vcs_cov_excl_files}",
"-report {cov_report_dir}"]
cov_report_txt: "{cov_report_dir}/dashboard.txt"
cov_report_page: "dashboard.html"
// Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
// GUI for visual analysis.
cov_analyze_dir: "{scratch_base_path}/cov_analyze"
cov_analyze_cmd: "{job_prefix} verdi"
cov_analyze_opts: ["-cov",
"-covdir {cov_merge_db_dir}",
"-line nocasedef"
"-elfile {vcs_cov_excl_files}"]
// Vars that need to exported to the env.
exports: [
VCS_ARCH_OVERRIDE: linux
VCS_LIC_EXPIRE_WARNING: 1
]
// Defaults for VCS
// By default, collect all coverage metrics.
cov_metrics: "line+cond+fsm+tgl+branch+assert"
// Supply the cov configuration file.
// Note that this needs to be set as -cm_hier <file>.
vcs_cov_cfg_file: ""
// Supply the cov configuration file for assertions.
// Note that this needs to be set as -cm_assert_hier <file>.
vcs_cov_assert_cfg_file: ""
// Supply the cov exclusion files.
vcs_cov_excl_files: []
// pass and fail patterns
build_fail_patterns: ["^Error-.*$"]
run_fail_patterns: ["^Error-.*$"] // Null pointer error
build_modes: [
{
name: vcs_waves
is_sim_mode: 1
build_opts: ["-debug_access+all"]
}
{
name: vcs_cov
is_sim_mode: 1
build_opts: [// Enable the required cov metrics
"-cm {cov_metrics}",
// Set the coverage hierarchy
"{vcs_cov_cfg_file}",
// Set the assert coverage hierarchy
"{vcs_cov_assert_cfg_file}",
// Cover all continuous assignments
"-cm_line contassign",
// Dump toggle coverage on mdas, array of structs and on ports only
"-cm_tgl mda+structarr+portsonly",
// Ignore initial blocks for coverage
"-cm_report noinitial",
// Filter unreachable/statically constant blocks
"-cm_noconst",
// Don't count coverage that's coming from zero-time glitches
"-cm_glitch 0",
// Ignore warnings about not applying cm_glitch to path and FSM
"+warn=noVCM-OPTIGN",
// Coverage database output location
"-cm_dir {cov_db_dir}"]
run_opts: [// Enable the required cov metrics
"-cm {cov_metrics}",
// Same directory as build
"-cm_dir {cov_db_dir}",
// Don't output cm.log which can be quite large
"-cm_log /dev/null",
// Provide a name to the coverage collected for this test
"-cm_name {cov_db_test_dir_name}"]
}
{
name: vcs_xprop
is_sim_mode: 1
build_opts: ["-xprop={tool_srcs_dir}/xprop.cfg"]
}
{
name: vcs_profile
is_sim_mode: 1
build_opts: ["-simprofile"]
run_opts: ["-simprofile {profile}"]
}
{
name: vcs_loopdetect
is_sim_mode: 1
build_opts: ["+vcs+loopreport", "+vcs+loopdetect"]
run_opts: ["+vcs+loopreport", "+vcs+loopdetect"]
}
]
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
build_cmd: "{job_prefix} xrun"
run_cmd: "{job_prefix} xrun"
// Indicate the tool specific helper sources - these are copied over to the
// {tool_srcs_dir} before running the simulation.
tool_srcs: ["{dv_root}/tools/xcelium/*"]
build_opts: ["-elaborate -64bit -access +r -sv",
"-licqueue",
// TODO: duplicate primitives between OT and Ibex #1231
"-ALLOWREDEFINITION",
"-messages -errormax 50",
"-timescale 1ns/1ps",
"-f {sv_flist}",
"-uvmhome CDNS-1.2",
"-xmlibdirname {build_dir}/xcelium.d",
// for uvm_hdl_* used by csr backdoor
"-access +rw",
"+define+XCELIUM",
]
run_opts: ["-input {tool_srcs_dir}/xcelium.tcl",
"-licqueue",
"-64bit -xmlibdirname {build_dir}/xcelium.d -R",
"+SVSEED={seed}",
"+UVM_TESTNAME={uvm_test}",
"+UVM_TEST_SEQ={uvm_test_seq}"]
// Vars that need to exported to the env.
exports: [
// Poll for an available license in all servers.
CDS_LIC_QUEUE_POLL: 1
// Poll for an available license every 1 min.
CDS_LIC_QUEUE_POLL_INT: 60
// X-prop related: these were suggested by Xcelium as warnings during the build time.
// These enable array corruption when the index is out of range or invalid.
VL_ENABLE_INVALID_IDX_XPROP: 1
VL_ENABLE_OUTOFRANGE_IDX_XPROP: 1
// Export the cov_report path so that the tcl file can read these as env vars.
cov_merge_db_dir: "{cov_merge_db_dir}"
cov_report_dir: "{cov_report_dir}"
]
// Coverage related.
// By default, collect all coverage metrics: block:expr:fsm:toggle:functional.
cov_metrics: all
// Supply the cov configuration file.
// Note that this needs to be set as -covfile <file>.
xcelium_cov_cfg_file: ""
// Supply the cov refinement files.
// Note that this needs to be set as -load_refinement <file>.
xcelium_cov_refine_files: [""]
// Set the coverage directories.
cov_work_dir: "{scratch_path}/coverage"
cov_db_dir: "{cov_work_dir}/{build_mode}"
// Individual test specific coverage data - this will be deleted if the test fails
// so that coverage from failiing tests is not included in the final report.
cov_db_test_dir_name: "{run_dir_name}.{seed}"
cov_db_test_dir: "{cov_db_dir}/{cov_db_test_dir_name}"
// Merging coverage.
// It is constructed by the tool itself.
cov_merge_dir: "{scratch_base_path}/cov_merge"
cov_merge_db_dir: "{cov_merge_dir}/merged"
cov_merge_cmd: "{job_prefix} imc"
cov_merge_opts: ["-64bit",
"-licqueue",
"-exec {tool_srcs_dir}/cov_merge.tcl"]
// Generate covreage reports in text as well as html.
cov_report_dir: "{scratch_base_path}/cov_report"
cov_report_cmd: "{job_prefix} imc"
cov_report_opts: ["-64bit",
"-licqueue",
"-exec {tool_srcs_dir}/cov_report.tcl",
"{xcelium_cov_refine_files}"]
cov_report_txt: "{cov_report_dir}/cov_report.txt"
cov_report_page: "index.html"
// Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
// GUI for visual analysis.
cov_analyze_dir: "{scratch_base_path}/cov_analyze"
cov_analyze_cmd: "{job_prefix} imc"
cov_analyze_opts: ["-gui",
"-64bit",
"-licqueue",
"-load {cov_merge_db_dir}",
"{xcelium_cov_refine_files}"]
// pass and fail patterns
build_fail_patterns: ["\\*E.*$"]
run_fail_patterns: ["\\*E.*$"] // Null pointer error
build_modes: [
{
name: xcelium_waves
is_sim_mode: 1
}
{
name: xcelium_cov
is_sim_mode: 1
build_opts: [// Enable the required cov metrics.
"-coverage {cov_metrics}",
// Limit the scope of coverage collection to the DUT.
"-covdut {dut}",
// Set the coverage configuration file.
"{xcelium_cov_cfg_file}"]
run_opts: [// Coverage database output location.
"-covworkdir {cov_work_dir}",
// Set the scope to the build mode name.
"-covscope {build_mode}",
// Test coverage dir name to create under cov_db_dir.
"-covtest {cov_db_test_dir_name}",
// Overwrite the coverage data of a specific test/seed if it already exists.
"-covoverwrite"]
}
// TODO support profile for xcelium
{
name: xcelium_profile
is_sim_mode: 1
build_opts: []
run_opts: []
}
{
name: xcelium_xprop
is_sim_mode: 1
build_opts: ["-xprop F -xverbose"]
}
{
// TODO: Add build and run options to enable zero delay loop detection.
name: xcelium_loopdetect
is_sim_mode: 1
build_opts: []
run_opts: []
}
]
}

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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# directory paths
# _ROOT are paths indicating a 'starting point'
# _PATH paths are intermediate paths leading to a _DIR
# _LOC are directory names without the hierarchy
# _DIR paths are final paths used in make rules
# All these variables can be overridden from the command line
# Test Makefile needs to set DV_DIR, DUT_TOP, TB_TOP, FUSESOC_CORE, COMPILE_KEY and TEST_NAME
# at minimum
export SHELL := /bin/bash
TIMESTAMP ?= $(shell date +%m.%d.%y_%H.%M.%S)
MAKE_ROOT := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
export PROJ_ROOT := ${MAKE_ROOT}/../../..
export PRJ_DIR := ${PROJ_ROOT}
export CURR_DIR := $(shell pwd)
SCRATCH_ROOT ?= ${DV_DIR}/scratch
SCRATCH_LOC ?= ${DUT_TOP}
BUILD_LOC ?= ${COMPILE_KEY}
RUN_LOC ?= ${TIMESTAMP}
SCRATCH_PATH ?= ${SCRATCH_ROOT}/${SCRATCH_LOC}
BUILD_DIR := ${SCRATCH_PATH}/${BUILD_LOC}
RUN_PATH ?= ${SCRATCH_PATH}/${TEST_NAME}
RUN_DIR := ${RUN_PATH}/${RUN_LOC}
COV_REPORT_DIR ?= ${SCRATCH_PATH}/cov_report
SW_BUILD_DIR ?= ${RUN_DIR}/sw_build
SW_ROOT_DIR := ${PRJ_DIR}/sw
SW_BUILD_DEVICE ?= fpga_nexysvideo
JOB_OPTS ?=
BUILD_JOB_OPTS ?= $(JOB_OPTS)
RUN_JOB_OPTS ?= $(JOB_OPTS)
# limit run directories upto a limit specified below
RUN_DIR_LIMIT ?= 5
# global simulation specific variables (but simulator independent)
SEED ?= $(shell od -vAn -N4 -tu < /dev/random | xargs)
BUILD_LOG ?= ${BUILD_DIR}/build.log
RUN_LOG ?= ${RUN_DIR}/run.log
UVM_VERBOSITY ?= UVM_LOW
TOPS ?= ${TB_TOP} ${DUT_TOP}_bind
# Options for SV build / C build / simulation run
# CL_ prefix represents command line versions of these options - they should be empty and only
# be set on the command line
# BUILD_OPTS are passed to the simulator during the SV testbench compile step
CL_BUILD_OPTS +=
BUILD_OPTS += $(addprefix -top , $(TOPS))
# RUN_OPTS are passed to the simulation executable that is invoked to run the simulation
CL_RUN_OPTS +=
RUN_OPTS += +UVM_NO_RELNOTES
# SW_OPTS are options for SW apps that come with their own Makefile (example coremark)
CL_SW_OPTS +=
SW_OPTS += ${CL_SW_OPTS}
# SW_FLAGS are compiler flags / directives that we can pass for each test using our own Makefiles
CL_SW_FLAGS +=
SW_FLAGS += ${CL_SW_FLAGS}
# default project-wide bus widths
TL_AW ?= 32
TL_DW ?= 32
TL_DBW ?= 4
# add auxiliary / helper mk files
# set simulator to vcs by default
SIMULATOR ?= vcs
# common tests/seqs
include ${MAKE_ROOT}/common_tests.mk
# tool to generate file list
include ${MAKE_ROOT}/fusesoc.mk
# modes / switches (option groups) that can be turned on easily
include ${MAKE_ROOT}/modes.mk
# add tool specific mk file
ifeq (${SIMULATOR},vcs)
include ${MAKE_ROOT}/vcs/vcs.mk
else ifeq (${SIMULATOR},xcelium)
include ${MAKE_ROOT}/xcelium/xcelium.mk
# else add other tool specific mk files
endif
# generic rules to sequence build and run flows
include ${MAKE_ROOT}/rules.mk

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# DV build and run flow
The Makefile system implemented here is a standardized solution for building and
running DV sims for all ip/block/top level testbenches. This is only a stop
gap solution until a proper build and run tool is developed and implemented. The
way the Makefiles are structured will hopefully make the eventual transition
easier.
## Makefile Organization
```
- hw/ip/<ip>/dv/Makefile OR
hw/top_earlgrey/dv/Makefile
- hw/dv/tools/Makefile
- ral_gen.mk
- fusesoc.mk
- modes.mk
- rules.mk
- vcs/vcs.mk # if SIMULATOR=vcs
- xcelium/xcelium.mk # if SIMULATOR=xcelium
```
### Test Makefile
The test Makefile that serves as the entry point into the DV build and run
flow is placed in individual 'dv' directories of each testbench. For example:
```hw/ip/uart/dv/Makefile```
This includes the top level Makefile, some mandatory variables that are to be
set and exported and the actual tests.
### Top level Makefile
This includes the top level Makefile which contains generic set of variable
names (most of which can be overridden) to indicate where, what and how to build
and run tests, some option groups and generic set of rules. This is located at
hw/dv/tools/Makefile
### Generic Tool-independent Make variables
The following is a list of Make variables that are used for specifying options
to run simulations in a tool-independent way. Some variables are overridable in
the Test Makefile (or command line) and some are appended to group / add options
together. Please see following table for more details:
Make variable | Description | Overridable (O) or Appendable (A) |
--------------|-------------|-----------------------------------|
DV_DIR | This is the top level DV directory for the IP containing the Test Makefile. | |
DUT_TOP | This is the top level dut module under test. | |
TB_TOP | This is the top level tb module under test. This is used by the `<simulator>.tcl` file when dumping waves. | |
FUSESOC_CORE | This is the testbench fusesoc .core name that contains the simulation target. This .core file is typically placed in the same directory as the test Makefile. | |
COMPILE_KEY | Users need to define COMPILE_KEY sets for building Test Makefile, CL with a unique sets of compile time options. This is to be done in the Test Makefile in this way: <br>`ifeq ($(COMPILE_KEY),foo)`<br> &emsp;`BUILD_OPTS += +define+FOO` <br>`endif`<br> There is a 'default' compile key already added which implies no additional compile time options are required. Within each test specification, the COMPILE_KEY can be overridden to use the specific compile key. <br>`ifeq ($(TEST_NAME),foo_test)`<br> &emsp;`COMPILE_KEY = foo` <br> &emsp;`# other test opts` <br>`endif` | O (Within tests, & command line) |
UVM_TEST | SV UVM test class to create in the test. This is set to the 'base_test' by default and is overridden in the test specifications if needed. | O (Test Makefile) |
UVM_TEST_SEQ | SV UVM test sequence to create in the test. This is set to the 'base_test' by default and is overridden in the test specifications if needed. | O (Test Makefile) |
TEST_NAME | Name of the test to run. These are specified in the test Makefile. By default, it is set to run the sanity test (simply calling 'make' will run this test). | O (command line only) |
SIMULATOR | What simulator to use. Currently only 'vcs' is supported and is set by default. | O |
BUILD_OPTS | Options to pass for build. | A (Test Makefile :: COMPILE_KEY specifications only) |
CL_BUILD_OPTS | Pass additional build options on the command line. | A (command line only) |
RUN_OPTS | Options to pass for run. | A (Test Makefile :: test specifications only) |
CL_RUN_OPTS | Pass additional run options on the command line. | A (command line only) |
WAVES | Enable wave dumps (fsdb). Set to 0 by default; override with WAVES=1. | O |
SIMPROFILE | Turn on sim profiling (time option by default). Set to 0 by default; override with SIMPROFILE=1. | O |
COV | Turn on coverage collection. Set to 0 by default; override with COV=1. | O |
UVM_VERBOSITY | Verbosity level for UVM. Set to UVM_LOW by default; override with UVM_VERBOSITY=UVM_NONE / UVM_LOW / UVM_HIGH / UVM_DEBUG. | O |
BUILD_LOC | Build directory name in the scratch area. This defaults to the COMPILE_KEY used by the corresponding test. You can override it to use a different directory name. This is helpful when there is a test / regression already running and you made some fixes and want to rerun some failing test from another terminal without affecting the existing running sims. | O |
RUN_LOC | Run directory name in the scratch area. This defaults to a 'timestamp' value. You can override this to a specific name. Everytime a test is run, it creates a new directory with the current timestamp for the name. By overriding this with a specific name and rerunning the same test with the same directory name, you won't have to reopen waves - you can just reload. This is useful during test debug. | O |
SCRATCH_ROOT | This is the path to the root scratch area for bulding and running tests. If SCRATCH_ROOT is not already set, it will create a `scratch` directory in `pwd` which typically is the same as `DV_DIR`. | O (command line only) |
RUN_DIR_LIMIT | When you run tests, The flow creates a new `RUN_LOC` directory with the current timestamp (unless it is overridden). In course of debug, you may run the same test multiple times, which will eventually result in a large number of old timestamp directories in the scratch space. Without periodic cleanup, you may run out of scratch space. By default, this variable is set to 5, which means before running the test, it will prune the test area to contain no more than RUN_DIR_LIMIT number of most recent directories (including the newly created one). On the flipside, if you want to run the same test with a large number of iterations, you will need to override this variable to be set to that many iterations to prevent the flow from deleting actively running simulations. | O (command line only) |
SEED | This is a run time parameter passed to the sim executable. It uses `od` command to generate a 32-bit random number to run the sim with a unique seed. You can override this variable on the command line to run the test with a specific seed for debug. | O (command line only) |
XPROP | This is a compile time parameter to enable / disable X-Propagation. Set to 1 by default. | O (command line only) |
This is not an exhaustive list of Make variables. Please see `./Makefile` and
`./*.mk` for more such variables in use.
### ral_gen.mk
#### RAL generation tool specific mk file
This lists tools and options to generate the ral model by simply running the
command `make ral` from the same directory as the Test Makefile. For generating
the UVM REG based RAL model, we use the same [in-house tool]({{< relref "doc/rm/register_tool" >}}) for autogenerating
RTL with mako template.
### fusesoc.mk
#### RTL/TB filelist generation tool specific mk file
This lists tools and options to generate the flattened filelist to supply to the
simulator during the build step.
### modes.mk
#### Modes or option groups that can be turned on easily
This lists common modes (which are groups of compile time and / or run time options)
passed to the simulator for turning on a specific function. Modes listed in this
file are meant to be common across all environments and simulator tools. Modes added
in this file are `WAVES`, `COV`, `SIMPROFILE` and `UVM_TRACE`. These are truly
global and can be turned on easily on the command line by setting them to 1: `COV=1`
switch on the command line will turn on coverage. These modes may require options
that are specific to the simulator tool, so the make variable `SIMULATOR` can be used
to set tool specific options.
### rules.mk
#### List of Make targets and recipes
This is the only file in the make flow that contains targets and recipes that
are completely agnostic to the tools used. It sequences the build and run set
of targets.
### Simulator mk ({vcs, xcelium}.mk)
#### Simulator tool specific options
The top level Makefile uses `SIMULATOR` variable (which is set to `vcs` by
default) to enable tool specific options. If support for new tools need to be
added, then those tool specific mk files need to be supplied. It sets the
following mandatory variables - `SIMCC` & `SIMX`. It also exports additional
tool specific variables to the sub shell when the recipes are executed. This
file has been placed in the respective tool directory.
### Simulation targets
* **build**: Compile and elaborate the testbench
* **gen_sv_flist**: Generate the full file list which will be used by the
simulator to build the simulation executable
* **run**: Run the test (the simulation executable needs to be built already)
* **env/\<ip\>_reg_block.sv**: Generate the RAL model only
* **sw_build**: Only compile the C SW test
### Building and running tests
All of the below command examples are to be run from the 'dv' directory
containing the Test Makefile.
##### Run the following command to build and run tests:
```console
$ make TEST_NAME=[test-name] [overrides]
```
##### To only buld the simv:
```console
$ make build TEST_NAME=[test-name] [overrides]
```
##### To run the sim after build is complete:
```console
$ make run TEST_NAME=[test-name] [overrides]
```
##### To build and run the sanity test:
```console
$ make
```
This will work provided user has specified a set a 'default' value to the
`TEST_NAME` Make variable.
##### Below are some examples
###### Build and run a test:
This builds the 'default' compile key and runs the 'uart_sanity' test
```console
$ make TEST_NAME=uart_sanity
```
###### Run with specific seed:
```console
$ make TEST_NAME=<test-name> SEED=123423334
```
###### Dump waves:
```console
$ make TEST_NAME=<test-name> SEED=123423334 WAVES=1
```
###### Run with coverage option enabled:
```console
$ make TEST_NAME=<test-name> COV=1
```
The options.mk file lists several tool options passed to the build and run steps
for enabling coverage collection. One of the options is adding a hier file (with
a `-cm_hier` switch). By default, it looks for a file called `cover.cfg` in the
'dv' directory set using the `CM_HIER` Make variable - if it exists, it adds the
switch automatically when coverage is enabled. If another hier file is desired
(or with another name), it can be placed anywhere as the user desires and user can
add the following line to the Test Makefile:
```gnumake
CM_HIER := <path-to-hier-file
```
###### Enable sim profiling:
```console
$ make TEST_NAME=<test-name> SIMPROFILE=1
```
###### Override UVM verbosity:
```console
$ make TEST_NAME=<test-name> WAVES=1 UVM_VERBOSITY=UVM_DEBUG
```
###### Build only (This will build the 'default' compile key):
```console
$ make build
```
###### Build 'foo' compile key instead:
```console
$ make build COMPILE_KEY=foo
```
###### Build with 'FOO' preprocessor flag:
```console
$ make build CL_BUILD_OPTS+=+define+FOO
```
###### Run with 'FOO' runtime plusarg:
```console
$ make TEST_NAME=<test-name> CL_RUN_OPTS+=+FOO
```
###### Run test with Xcelium:
```
$ make TEST_NAME=<test-name> SIMULATOR=xcelium
```
###### Run test with Xcelium and dump WAVES in fsdb:
```console
$ make TEST_NAME=<test-name> SIMULATOR=xcelium WAVES=1
```
###### Run test with Xcelium and dump WAVES in shm:
```console
$ make TEST_NAME=<test-name> SIMULATOR=xcelium WAVES=1 DUMP=shm
```
###### Run only (This assumes the sim executable for the specified compile key is available):
```console
$ make run TEST_NAME=<test-name> SEED=123423334 WAVES=1
```

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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Makefile option groups that can be enabled by test Makefile / command line.
# These are generic set of option groups that apply to all testbenches.
# These are meant to be simulator agnostic
# Please add tool specific options with appropriate ifeq's
TEST_PREFIX ?= ${DUT_TOP}
ifeq (${TEST_NAME},${TEST_PREFIX}_csr_hw_reset)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_csr_rw)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_csr_bit_bash)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_csr_aliasing)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_same_csr_outstanding)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +run_same_csr_outstanding
RUN_OPTS += +en_scb=0
endif
# make sure DUT has memory and support this seq before run the test
ifeq (${TEST_NAME},${TEST_PREFIX}_csr_mem_walk)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +csr_mem_walk
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_tl_errors)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +run_tl_errors
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_intr_test)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +run_intr_test
endif
ifeq (${TEST_NAME},${TEST_PREFIX}_stress_all_with_rand_reset)
UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
RUN_OPTS += +run_stress_all_with_rand_reset
// 10ms
RUN_OPTS += +test_timeout_ns=10000000000
RUN_OPTS += +stress_seq=${TEST_PREFIX}_stress_all_vseq
endif

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^TEST FAILED (UVM_)?CHECKS$
^UVM_ERROR\s[^:].*$
^\s*Offending '.*'

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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Make variables specific to FUSESOC tool used for generating the filelist
# The following Make variables are to be set in the Test Makefile
# FUSESOC_CORE: the top level fusesoc core file developed for the ip/top level testbench
# see hw/ip/uart/dv/uart_sim.core as an example
# Rest of the Make variables added here are intermeditiate ones used in the flow
# fusesoc tool and options
SV_FLIST_GEN_TOOL ?= fusesoc
SV_FLIST_GEN_OPTS += --cores-root ${PROJ_ROOT} --cores-root ${RAL_MODEL_DIR} \
run --target=sim --setup ${FUSESOC_CORE}
FUSESOC_CORE_ = $(shell echo "${FUSESOC_CORE}" | tr ':' '_')
SV_FLIST_GEN_DIR = ${BUILD_DIR}/build/${FUSESOC_CORE_}/sim-vcs
SV_FLIST := ${SV_FLIST_GEN_DIR}/${FUSESOC_CORE_}.scr

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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Makefile option groups that can be enabled by test Makefile / command line.
# These are generic set of option groups that apply to all testbenches.
# These are meant to be simulator agnostic
# Please add tool specific options with appropriate ifeq's
# Distinguish UVM TB and the other environments for Verilator, FPGA etc
BUILD_OPTS += +define+UVM
# uvm specific - set default widths
BUILD_OPTS += +define+UVM_NO_DEPRECATED
BUILD_OPTS += +define+UVM_REGEX_NO_DPI
BUILD_OPTS += +define+UVM_REG_ADDR_WIDTH=${TL_AW}
BUILD_OPTS += +define+UVM_REG_DATA_WIDTH=${TL_DW}
BUILD_OPTS += +define+UVM_REG_BYTENABLE_WIDTH=${TL_DBW}
# Enable UVM trace options
UVM_TRACE ?= 0
ifeq (${UVM_TRACE},1)
RUN_OPTS += +UVM_PHASE_TRACE
RUN_OPTS += +UVM_CONFIG_DB_TRACE
RUN_OPTS += +UVM_OBJECTION_TRACE
endif
# Options for generating waves / debugging.
WAVES ?= 0
DUMP ?= fsdb
DUMP_FILE ?= waves.${DUMP}
export WAVES
export DUMP
export DUMP_FILE
ifeq (${WAVES},1)
ifeq (${SIMULATOR},vcs)
VCS_WAVES = 1
endif
endif
# Enable simulation profiling
SIMPROFILE ?= 0
ifeq (${SIMPROFILE},1)
ifeq (${SIMULATOR},vcs)
VCS_SIMPROFILE = 1
else ifeq (${SIMULATOR},xcelium)
XCELIUM_SIMPROFILE = 1
endif
endif
# Enable coverage
COV ?= 0
ifeq (${COV},1)
ifeq (${SIMULATOR},vcs)
VCS_COV = 1
else ifeq (${SIMULATOR},xcelium)
XCELIUM_COV = 1
endif
endif

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#!/usr/bin/env bash
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# this script checks for test pass/fail signatures at the end of the test
usage="Error: usage: $0 [path-to-run-log] [path-to-pass-patterns] [path-to-fail-patterns]";
# need exactly 1 args (path to the run.log)
if [[ $# -ne 3 || ! -f $1 || ! -f $2 || ! -f $3 ]]; then
echo $usage
exit 1;
fi
# none of the fail patterns should be present
while ifs= read -r fail_pattern; do
grep_cmd="grep -c -m 1 -E '$fail_pattern' $1";
fail_pattern_found=$(eval $grep_cmd);
if [[ $fail_pattern_found -ne 0 ]]; then
echo "Fail pattern '$fail_pattern' found"
exit 1
fi
done < $3
# all pass patterns should be present
while ifs= read -r pass_pattern; do
grep_cmd="grep -c -m 1 -E '$pass_pattern' $1";
pass_pattern_found=$(eval $grep_cmd);
if [[ $pass_pattern_found -eq 0 ]]; then
echo "Pass pattern '$pass_pattern' not found"
exit 1
fi
done < $2

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^TEST PASSED (UVM_)?CHECKS$

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# `ralgen`: A FuseSoC generator for UVM RAL package
The `ralgen.py` script is implemented as a
[FuseSoC generator](https://fusesoc.readthedocs.io/en/master/user/generators.html).
which enables the automatic creation of the SystemVerilog UVM RAL package and
its insertion into the dependency tree when compiling the DV testbench.
This approach is useful for DV simulation flows that use FuseSoC as the backend
to generate the filelist for compilation. A separate RAL package generation
step is no longer needed since it gets handled within FuseSoC.
## Generator
The adjoining `ralgen.core` file registers the `ralgen` generator. The FuseSoC
core file that 'calls' the generator adds it as a dependency. When calling the
generator, the following parameters are set:
* **name (mandatory)**: Name of the RAL package (typically, same is the IP).
* **ip_hjson**: Path to the hjson specification written for an IP which includes
the register descriptions. This needs to be a valid input for `reggen`.
* **top_hjson**: Path to the hjson specification for a top level design. This
needs to be a valid input for `topgen`.
Only one of the last two arguments is mandatory. If both are set, or if neither
of them are, then the tool throws an error and exits.
The following snippet shows how it is called:
```
generate:
ral:
generator: ralgen
parameters:
name: <name>
<ip_hjson|top_hjson>: <path-to-hjson-spec>
targets:
default:
...
generate:
- ral
```
Note that the path to `hjson` specification in the snippet above is relative
to the core file in which the generator is called.
## `ralgen` script
When FuseSoC processes the dependency list and encounters a generator, it
passes a YAML file containing the above parameters to the generator tool
(the `ralgen.py`) as a single input. It then parses the YAML input to
extract those parameters.
`ralgen.py` really is just a wrapper around
[`reggen`]({{< relref "util/reggen/README.md" >}}) and the `util/topgen.py`
scripts, which are the ones that actually create the RAL package.
Due to the way those scripts are implemented, RAL packages for the IP level
testbenches are generated using
[`reggen`](({{< relref "util/reggen/README.md" >}})), and for the chip level
testbench, `util/topgen.py`. Which one to choose is decided by whether
the `ip_hjson` or `top_hjson` parameter is supplied.
In addition, the `ralgen.py` script also creates a FuseSoC core file. It uses
the `name` parameter to derive the
[VLNV](https://fusesoc.readthedocs.io/en/master/user/overview.html#core-naming-rules)
name for the generated core file.
The generated core file adds **`lowrisc:dv:dv_lib`** as a dependency for the
generated RAL package. This is required because our DV register block, register
and field models are derived from the
[DV library]({{< relref "hw/dv/sv/dv_lib/README.md" >}}) of classes. This
ensures the right compilation order is maintained.
## Limitations
The script is not designed to be manually invoked, but in theory, it can be, if
a YAML file that contains the right set of parameters is presented to it
(compliant with FuseSoC).
If the user wishes to create the RAL package manually outside of the DV
simulation flow, then the `make` command can be invoked in the `hw/'` area
instead. It generates the RTL, DV and SW collaterals for all IPs, as well as
the top level in a single step.

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CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:ralgen"
description: "Generator for UVM RAL package used in DV testbenches."
generators:
ralgen:
interpreter: python3
command: ralgen.py

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#!/usr/bin/env python3
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
r"""FuseSoc generator for UVM RAL package created with either regtool or
topgen tools.
"""
import argparse
import os
import subprocess
import sys
import yaml
try:
from yaml import CSafeLoader as YamlLoader, CSafeDumper as YamlDumper
except ImportError:
from yaml import SafeLoader as YamlLoader, SafeDumper as YamlDumper
# Repo root is 4 levels up. Note that this will require an update if the path to
# this tool is changed.
REPO_ROOT = "../../../.."
# Given a root dir and partial path, this function returns the full path.
def get_full_path(root_dir, partial_path):
full_path = os.path.abspath(os.path.join(root_dir, partial_path))
if not os.path.exists(full_path):
print("Error: path appears to be invalid: {}".format(full_path))
sys.exit(1)
return full_path
def main():
if len(sys.argv) != 2:
print("ERROR: This script takes a single YAML file as input argument")
sys.exit(1)
gapi_filepath = sys.argv[1]
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
# This is just a wrapper around the reggen and topgen tools, which
# are referenced from proj_root area.
self_path = os.path.dirname(os.path.realpath(__file__))
util_path = os.path.abspath(os.path.join(self_path, REPO_ROOT, "util"))
# Retrieve the parameters from the yml.
root_dir = gapi['files_root']
name = gapi['parameters'].get('name')
ip_hjson = gapi['parameters'].get('ip_hjson')
top_hjson = gapi['parameters'].get('top_hjson')
if not name or (bool(ip_hjson) == bool(top_hjson)):
print("Error: ralgen requires the \"name\" and exactly one of "
"{\"ip_hjson\" and \"top_hjson\"} parameters to be set.")
sys.exit(1)
# Generate the RAL pkg.
ral_pkg_file = name + "_ral_pkg.sv"
if ip_hjson:
ral_spec = get_full_path(root_dir, ip_hjson)
cmd = os.path.join(util_path, "regtool.py")
args = [cmd, "-s", "-t", ".", ral_spec]
else:
ral_spec = get_full_path(root_dir, top_hjson)
cmd = os.path.join(util_path, "topgen.py")
args = [cmd, "-r", "-o", ".", "-t", ral_spec]
try:
subprocess.run(args, check=True)
except subprocess.CalledProcessError as e:
print("Error: RAL pkg generation failed:\n{}".format(str(e)))
sys.exit(e.returncode)
print("RAL pkg file written to {}".format(os.path.abspath(ral_pkg_file)))
# Generate the FuseSoc core file.
ral_pkg_core_text = {
'name': "lowrisc:dv:{}_ral_pkg".format(name),
'filesets': {
'files_dv': {
'depend': [
"lowrisc:dv:dv_base_reg",
],
'files': [
ral_pkg_file,
],
'file_type': 'systemVerilogSource'
},
},
'targets': {
'default': {
'filesets': [
'files_dv',
],
},
},
}
ral_pkg_core_file = os.path.abspath(name + "_ral_pkg.core")
with open(ral_pkg_core_file, 'w') as f:
f.write("CAPI=2:\n")
yaml.dump(ral_pkg_core_text,
f,
encoding="utf-8",
default_flow_style=False,
sort_keys=False)
print("RAL core file written to {}".format(ral_pkg_core_file))
if __name__ == '__main__':
main()

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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
.DEFAULT_GOAL := all
all: build run
###############################
## sim build and run targets ##
###############################
build: compile_result
pre_compile:
mkdir -p ${BUILD_DIR} && \
env > ${BUILD_DIR}/env_vars
gen_sv_flist: pre_compile
cd ${BUILD_DIR} && ${SV_FLIST_GEN_TOOL} ${SV_FLIST_GEN_OPTS}
compile: gen_sv_flist
cd ${SV_FLIST_GEN_DIR} && $(BUILD_JOB_OPTS) ${SIMCC} ${BUILD_OPTS} ${CL_BUILD_OPTS}
post_compile: compile
compile_result: post_compile
run: run_result
pre_run:
rm -rf ${RUN_PATH}/latest
mkdir -p ${RUN_DIR}
ln -s ${RUN_DIR} ${RUN_PATH}/latest
/bin/bash ${MAKE_ROOT}/run_dir_limiter ${RUN_PATH} ${RUN_DIR_LIMIT}
env > ${RUN_DIR}/env_vars
sw_build: pre_run
ifneq (${SW_NAME},)
# NOTE: Pass -f, since we're going to be re-building everything every time,
# anyways.
cd $(PROJ_ROOT) && \
BUILD_ROOT=$(SW_BUILD_DIR) $(PROJ_ROOT)/meson_init.sh -f
# NOTE: We're using the fpga platform for now, because there is no
# such thing as a DV platform yet (nor does any code do anything
# special for DV yet).
ninja -C $(SW_BUILD_DIR)/build-out sw/device/boot_rom/boot_rom_export_$(SW_BUILD_DEVICE)
ninja -C $(SW_BUILD_DIR)/build-out sw/device/$(SW_DIR)/$(SW_NAME)_export_$(SW_BUILD_DEVICE)
mkdir -p $(SW_BUILD_DIR)/sw $(SW_BUILD_DIR)/rom
cp $(SW_BUILD_DIR)/build-out/sw/device/boot_rom/boot_rom_$(SW_BUILD_DEVICE).vmem \
$(SW_BUILD_DIR)/rom/rom.vmem
cp $(SW_BUILD_DIR)/build-out/sw/device/$(SW_DIR)/$(SW_NAME)_$(SW_BUILD_DEVICE).vmem \
$(SW_BUILD_DIR)/sw/sw.vmem
endif
simulate: sw_build
cd ${RUN_DIR} && $(RUN_JOB_OPTS) ${SIMX} ${RUN_OPTS} ${CL_RUN_OPTS}
post_run: simulate
run_result: post_run
/bin/bash ${MAKE_ROOT}/pass_fail ${RUN_LOG} ${MAKE_ROOT}/pass_patterns ${MAKE_ROOT}/fail_patterns
############################
## coverage rated targets ##
############################
cov_merge:
# TODO: add script to merge coverage in scratch scope
# open coverage tool to review and create report or exclusion file
cov_analyze:
cd ${SCRATCH_PATH} && ${COV_ANALYZE_TOOL} ${COV_ANALYZE_OPTS}
# generate coverage report directly
cov_report:
cd ${SCRATCH_PATH} && ${COV_REPORT_TOOL} ${COV_REPORT_OPTS}
clean:
rm -rf ${SCRATCH_PATH}/*
.PHONY: ral \
build \
run \
reg \
pre_compile \
compile \
post_compile \
compile_result \
sw_build \
pre_run \
simulate \
post_run \
run_result \
cov_merge \
cov_analyze \
cov_report \
clean

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#!/usr/bin/env bash
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# run_dir_limiter does what the name suggests - often, when tests are run multiple times, the number
# of run directories created might end up getting large. This script finds and deletes N oldest
# directories in a given path P, where P and N are the arguments to this script respedtively
usage="Error: usage: $0 [path-to-run-dir] [num-run-dir-limit]";
# need exactly 2 args, 1st needs to be the path and 2nd, a number
if [[ $# -ne 2 || ! -d $1 || ! $2 =~ ^[0-9]+$ ]]; then
echo $usage
exit 1;
fi
run_dir=$(realpath $1);
find_cmd="find $run_dir -mindepth 1 -maxdepth 1 -type d";
num_dirs=$($find_cmd | wc -l);
num_rm_dirs=$(($num_dirs - $2));
if [[ $num_rm_dirs -gt 0 ]]; then
dirs=$($find_cmd -printf '%T+ %p\n' | sort | head -n $num_rm_dirs | awk '{print $2}');
for dir in $dirs; do
echo "Removing $dir..."
/bin/rm -rf $dir
done
fi

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: csr_hw_reset
desc: '''
Verify the reset values as indicated in the RAL specification.
- Write all CSRs with a random value.
- Apply reset to the DUT as well as the RAL model.
- Read each CSR and compare it against the reset value.
it is mandatory to replicate this test for each reset that affects
all or a subset of the CSRs.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
'''
milestone: V1
tests: ["{name}{intf}_csr_hw_reset"]
}
{
name: csr_rw
desc: '''
Verify accessibility of CSRs as indicated in the RAL specification.
- Loop through each CSR to write it with a random value.
- Read the CSR back and check for correctness while adhering to its
access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
'''
milestone: V1
tests: ["{name}{intf}_csr_rw"]
}
{
name: csr_bit_bash
desc: '''
Verify no aliasing within individual bits of a CSR.
- Walk a 1 through each CSR by flipping 1 bit at a time.
- Read the CSR back and check for correctness while adhering to its
access policies.
- This verify that writing a specific bit within the CSR did not affect
any of the other bits.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
'''
milestone: V1
tests: ["{name}{intf}_csr_bit_bash"]
}
{
name: csr_aliasing
desc: '''
Verify no aliasing within the CSR address space.
- Loop through each CSR to write it with a random value
- Shuffle and read ALL CSRs back.
- All CSRs except for the one that was written in this iteration should
read back the previous value.
- The CSR that was written in this iteration is checked for correctness
while adhering to its access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
'''
milestone: V1
tests: ["{name}{intf}_csr_aliasing"]
}
{
name: csr_mem_rw_with_rand_reset
desc: '''
Verify random reset during CSR/memory access.
- Run csr_rw sequence to randomly access CSRs
- If memory exists, run mem_partial_access in parallel with csr_rw
- Randomly issue reset and then use hw_reset sequence to check all CSRs
are reset to default value
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
'''
milestone: V1
tests: ["{name}{intf}_csr_mem_rw_with_rand_reset"]
}
]
}

19
vendor/lowrisc_ip/dv/tools/testplans/enable_reg_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: enable_reg
desc: '''
The CSR test sequences will read and write accessible CSRs including the enable
registers and their locked registers. The RAL model supports predicting the correct
value of the locked registers based on their enable registers.
'''
milestone: V2
tests: ["{name}{intf}_csr_rw",
"{name}{intf}_csr_bit_bash",
"{name}{intf}_csr_aliasing"]
}
]
}

18
vendor/lowrisc_ip/dv/tools/testplans/fpv_csr_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: fpv_csr_rw
desc: '''
Write assertions to verify all the CSRs from the TileLink. Each CSR will include a read
assertion to ensure the read value from the TileLink is expected, and a write assertion
to ensure the write value is updated correctly to DUT according to the register's access.
'''
milestone: V2
tests: ["{name}{intf}_fpv_csr_rw"]
}
]
}

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vendor/lowrisc_ip/dv/tools/testplans/intr_test_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: intr_test
desc: '''
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
- Enable a random set of interrupts by writing random value(s) to
intr_enable CSR(s).
- Randomly "turn on" interrupts by writing random value(s) to intr_test
CSR(s).
- Read all intr_state CSR(s) back to verify that it reflects the same value
as what was written to the corresponding intr_test CSR.
- Check the cfg.intr_vif pins to verify that only the interrupts that were
enabled and turned on are set.
- Clear a random set of interrupts by writing a randomly value to intr_state
CSR(s).
- Repeat the above steps a bunch of times.
'''
milestone: V2
tests: ["{name}{intf}_intr_test"]
}
]
}

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vendor/lowrisc_ip/dv/tools/testplans/mem_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: mem_walk
desc: '''
Verify accessibility of all memories in the design.
- Run the standard UVM mem walk sequence on all memories in the RAL model.
- It is mandatory to run this test from all available interfaces the
memories are accessible from.
'''
milestone: V1
tests: ["{name}{intf}_mem_walk"]
}
{
name: mem_partial_access
desc: '''
Verify partial-accessibility of all memories in the design.
- Do partial reads and writes into the memories and verify the outcome for
correctness.
- Also test outstanding access on memories
'''
milestone: V1
tests: ["{name}{intf}_mem_partial_access"]
}
// TODO: add mem access with reset
]
}

31
vendor/lowrisc_ip/dv/tools/testplans/shadow_reg_errors_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
// this testplan should be imported by all IPs containing shadowed CSRs
name: shadow_reg_errors
desc: '''
Verify shadow registers' update and storage errors.
- Issue reset at random to clear all the internal stored values and phases trackers
in shadow registers.
- Select all the shadow registers and a random amount of the rest of the non-excluded
registers. Shuffle and write random values to the selected registers.
For shadow registers, the second write is not enabled.
There is a 50% possibility that the shadow register's write value is identical to its
previous write value.
If shadow register's second write value does not match the first write value,
ensure that the update error alert is triggered.
- Randomly inject storage errors by modifying the shadow register's staged or committed
values via backdoor method. Ensure that the storage error alert is triggered.
- Randomly decide to read all the non-excluded registers or fields. Then check the read
values against predicted values.
A read on a shadow register will clear its phase tracker.
- Repeat the above steps a bunch of times.
'''
milestone: V1
tests: ["{name}_shadow_reg_errors"]
}
]
}

15
vendor/lowrisc_ip/dv/tools/testplans/stress_all_with_reset_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: stress_all_with_rand_reset
desc: '''This test runs 3 parallel threads - stress_all, tl_errors and random reset.
After reset is asserted, the test will read and check all valid CSR registers.
'''
milestone: V2
tests: ["{name}_stress_all_with_rand_reset"]
}
]
}

40
vendor/lowrisc_ip/dv/tools/testplans/tl_device_access_types_testplan.hjson vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
entries: [
{
name: oob_addr_access
desc: "Access out of bounds address and verify correctness of response / behavior"
milestone: V2
tests: ["{name}_tl_errors"]
}
{
name: illegal_access
desc: '''Drive unsupported requests via TL interface and verify correctness of response
/ behavior '''
milestone: V2
tests: ["{name}_tl_errors"]
}
{
name: outstanding_access
desc: '''Drive back-to-back requests without waiting for response to ensure there is one
transaction outstanding within the TL device. Also, verify one outstanding when back-
to-back accesses are made to the same address.'''
milestone: V2
tests: ["{name}{intf}_csr_hw_reset",
"{name}{intf}_csr_rw",
"{name}{intf}_csr_aliasing",
"{name}{intf}_same_csr_outstanding"]
}
{
name: partial_access
desc: '''Do partial accesses.'''
milestone: V2
tests: ["{name}{intf}_csr_hw_reset",
"{name}{intf}_csr_rw",
"{name}{intf}_csr_aliasing"]
}
]
}

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vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.el vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Exclude below TL toggle coverage as these pins won't be changed in the comportable IPs
INSTANCE: tb.dut
Toggle tl_i.a_user.parity "logic tl_i.a_user.parity[7:0]"
Toggle tl_i.a_user.parity_en "logic tl_i.a_user.parity_en"
Toggle tl_i.a_user.rsvd1 "logic tl_i.a_user.rsvd1[6:0]"
Toggle tl_o.d_opcode [1] "logic tl_o.d_opcode[2:0]"
Toggle tl_o.d_opcode [2] "logic tl_o.d_opcode[2:0]"
Toggle tl_o.d_param "logic tl_o.d_param[2:0]"
Toggle tl_o.d_sink "logic tl_o.d_sink[0:0]"
Toggle tl_o.d_user "logic tl_o.d_user[15:0]"
Toggle tl_i.a_param "logic tl_i.a_param[2:0]"

15
vendor/lowrisc_ip/dv/tools/vcs/cover.cfg vendored Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Enables coverage on the entire DUT. Limits the port only toggle coverage to
// the DUT IOs.
+tree tb.dut
-module pins_if // DV construct.
-module clk_rst_if // DV construct.
begin tgl
-tree tb
+tree tb.dut 1
end

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vendor/lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg vendored Normal file
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@ -0,0 +1,14 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Limits coverage collection only to the *_reg_top module and the TL interface
// of the DUT.
+moduletree *_reg_top
+node tb.dut tl_*
// Remove everything else from toggle coverage.
begin tgl
-tree tb
end

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vendor/lowrisc_ip/dv/tools/vcs/vcs.mk vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Makefile option groups that can be enabled by test Makefile / command line.
# These are generic set of option groups that apply to all testbenches.
# Simulator too specific options
# Mandatory items to set (these are used by rules.mk):
# SIMCC - Simulator compiler used to build / elaborate the bench
# SIMX - Simulator executable used to run the tests
SIMCC := vcs
SIMX ?= ${BUILD_DIR}/simv
SIM_SETUP ?= ${MAKE_ROOT}/vcs/vcs.tcl
# set standard build options
BUILD_OPTS += -sverilog -full64 -licqueue -timescale=1ns/1ps -kdb
BUILD_OPTS += -ntb_opts uvm-1.2
BUILD_OPTS += -Mdir=${BUILD_DIR}/simv.csrc
BUILD_OPTS += -l ${BUILD_LOG}
BUILD_OPTS += -o ${SIMX}
BUILD_OPTS += -f ${SV_FLIST}
BUILD_OPTS += +incdir+${BUILD_DIR}
BUILD_OPTS += -debug_access+pp
BUILD_OPTS += +warn=noUII-L
# turn on warnings if functions are called with return value ignored
BUILD_OPTS += +warn=SV-NFIVC
# option below is required for $error / $fatal system calls
BUILD_OPTS += -assert svaext
# Force DPI-C compilation in C99 mode
BUILD_OPTS += -CFLAGS "--std=c99"
# Without this magic LDFLAGS argument below, we get compile time errors with
# VCS on Google Linux machines that look like this:
# .../libvcsnew.so: undefined reference to `snpsReallocFunc'
# .../libvcsnew.so: undefined reference to `snpsCheckStrdupFunc'
# .../libvcsnew.so: undefined reference to `snpsGetMemBytes'
BUILD_OPTS += -LDFLAGS "-Wl,--no-as-needed"
# set standard run options
RUN_OPTS += -licqueue
RUN_OPTS += -ucli -do ${SIM_SETUP}
RUN_OPTS += +ntb_random_seed=${SEED}
RUN_OPTS += +UVM_VERBOSITY=${UVM_VERBOSITY}
RUN_OPTS += +UVM_TESTNAME=${UVM_TEST}
RUN_OPTS += +UVM_TEST_SEQ=${UVM_TEST_SEQ}
RUN_OPTS += -l ${RUN_LOG}
#########################
## Tool Specific Modes ##
#########################
# Enable simulation profiling
VCS_SIMPROFILE ?= 0
ifeq (${VCS_SIMPROFILE},1)
BUILD_OPTS += -simprofile
RUN_OPTS += -simprofile time
endif
# Enable waves
VCS_WAVES ?= 0
ifeq (${VCS_WAVES},1)
BUILD_OPTS += -debug_access+all
endif
# Enable coverage
VCS_COV ?= 0
ifeq (${VCS_COV},1)
COV_METRICS ?= line+cond+fsm+tgl+branch+assert
BUILD_OPTS += -cm ${COV_METRICS}
CM_HIER ?= ${MAKE_ROOT}/vcs/cover.cfg
# Add -cm_hier switch if ${CM_HIER} file exists
BUILD_OPTS += $(shell if [ -f ${CM_HIER} ]; then echo "-cm_hier ${CM_HIER}"; fi)
# Cover all continuous assignments
BUILD_OPTS += -cm_line contassign
# Dump toggle coverage on mdas, array of structs and on ports only
BUILD_OPTS += -cm_tgl mda+structarr+portsonly
# Ignore initial blocks for coverage
BUILD_OPTS += -cm_report noinitial
# Filter unreachable/statically constant blocks
BUILD_OPTS += -cm_noconst
# Don't count coverage that's coming from zero-time glitches
BUILD_OPTS += -cm_glitch 0
# Ignore warnings about not applying cm_glitch to path and FSM
BUILD_OPTS += "+warn=noVCM-OPTIGN"
# Coverage database output location
BUILD_OPTS += -cm_dir ${BUILD_DIR}/cov.vdb
RUN_OPTS += -cm ${COV_METRICS}
# Same directory as build
RUN_OPTS += -cm_dir ${BUILD_DIR}/cov.vdb
# Don't output cm.log which can be quite large
RUN_OPTS += -cm_log /dev/null
# Provide a name to the coverage collected for this test
RUN_OPTS += -cm_name ${TEST_NAME}_${RUN_LOC}_${SEED}
# Don't dump all the coverage assertion attempts at the end of simulation
RUN_OPTS += -assert nopostproc
endif
# Enable XPROP
XPROP ?= 1
ifeq (${XPROP},1)
VCS_XPROP_CFG_FILE ?= ${MAKE_ROOT}/vcs/xprop.cfg
BUILD_OPTS += -xprop=${VCS_XPROP_CFG_FILE}
endif
# Coverage analyze/report options
COV_COMMON_EXCL ?= ${MAKE_ROOT}/vcs/common_cov_excl.el
COV_EXCL += ${COV_COMMON_EXCL} ${COV_DUT_EXCL}
COV_ANALYZE_TOOL ?= verdi
COV_REPORT_TOOL ?= urg
COV_DIR ?= ${BUILD_DIR}/cov.vdb
COV_EXCL_OPTS ?= -line nocasedef -elfile ${COV_EXCL}
COV_ANALYZE_OPTS ?= -cov -covdir ${COV_DIR} ${COV_EXCL_OPTS}
COV_REPORT_OPTS ?= -dir ${COV_DIR} ${COV_EXCL_OPTS} -report ${COV_REPORT_DIR}
# env variables to be exported for VCS
export VCS_ARCH_OVERRIDE := linux
export VCS_LIC_EXPIRE_WARNING := 1

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vendor/lowrisc_ip/dv/tools/vcs/vcs.tcl vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# TCL file invoked from VCS's simv at run-time using this: -ucli -do <this file>
# Get some environment variables we need.
set en_waves 0
set tool_srcs_dir ""
if {[info exists ::env(EN_WAVES)]} {
set en_waves "$::env(EN_WAVES)"
}
if {[info exists ::env(TOOL_SRCS_DIR)]} {
set tool_srcs_dir "$::env(TOOL_SRCS_DIR)"
} else {
puts "ERROR: tool script run without TOOL_SRCS_DIR environment variable."
quit
}
# If wave dumping is enabled, run waves.tcl
if {"$en_waves" == 1} {
source "${tool_srcs_dir}/waves.tcl"
}
run
quit

4
vendor/lowrisc_ip/dv/tools/vcs/xprop.cfg vendored Normal file
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merge = xmerge;
// Turn on xprop for dut only
instance { tb.dut } { xpropOn };

45
vendor/lowrisc_ip/dv/tools/waves.tcl vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Generic TCL included by tool-specific scripts when wave dumping is
# enabled.
#
# This is used by all supported simulators, and the driver scripts
# (dvsim.py) need to make sure that we don't ask for an unsupported
# dumping format (SHM with VCS, for example).
#
set dump_fmt none
if {[info exists ::env(DUMP_FMT)]} {
set dump_fmt "$::env(DUMP_FMT)"
} else {
puts "ERROR: No DUMP_FMT specified for wave dumping."
quit
}
set tb_top "tb"
if {[info exists ::(TB_TOP)]} {
set tb_top "$::env(TB_TOP)"
}
if {"$dump_fmt" == "fsdb"} {
# The fsdbDumpvars +all command dumps everything: memories,
# MDA signals, structs, unions, power and packed structs.
puts "Dumping waves with VERDI to waves.fsdb"
fsdbDumpfile "waves.fsdb"
fsdbDumpvars 0 $tb_top +all
fsdbDumpSVA 0 $tb_top
} elseif {"$dump_fmt" == "shm"} {
puts "Dumping waves in SHM format to waves.shm"
database -open -default -shm "waves.shm"
probe "$tb_top" -all -depth all -shm
} elseif {"$dump_fmt" == "vpd"} {
puts "Dumping waves in VCD+ format to waves.vpd"
dump -file "waves.vpd"
dump -add "$tb_top" -depth 0 -aggregates -scope "."
} else {
puts "ERROR: Unknown dump format: ${dump_fmt}"
quit
}

21
vendor/lowrisc_ip/dv/tools/xcelium/cov_merge.tcl vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Merge coverage with IMC, across tests, scopes and previous regression runs.
# Set the input coverage directories across all available scopes and previous runs,
# using the env var 'cov_db_dirs' (which is a space separated list of directories).
# Append each of these directories with /* wildcard at the end to allow the tool to
# find all available test databases.
set cov_db_dirs_env [string trim $::env(cov_db_dirs) " \""]
foreach i $cov_db_dirs_env { append cov_db_dirs "[string trim $i]/* "; }
puts "Input coverage directories:\n$cov_db_dirs"
# Set the output directory for the merged database using the env var 'cov_merge_db_dir'.
# The supplied env var may have quotes or spaces that needs to be trimmed.
puts "Output directory for merged coverage:"
set cov_merge_db_dir [string trim $::env(cov_merge_db_dir) " \""]
# Run the merge command.
merge $cov_db_dirs -out $cov_merge_db_dir -overwrite

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vendor/lowrisc_ip/dv/tools/xcelium/cov_report.tcl vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Generate reports for the merged coverage in HTML and text format.
# Set the input merged coverage database directory using the env var 'cov_merge_db_dir'.
# The supplied env var may have quotes or spaces that needs to be trimmed.
set cov_merge_db_dir [string trim $::env(cov_merge_db_dir) " \""]
# Set the output directory for the reports database using the env var 'cov_report_dir'.
# The supplied env var may have quotes or spaces that needs to be trimmed.
set cov_report_dir [string trim $::env(cov_report_dir) " \""]
# Set the DUT name.
set dut [string trim $::env(DUT_TOP)]
set dut_uc [string toupper $dut]
set dut_instance [string trim $::env(dut_instance)]
# Load the merged coverage database.
load -run $cov_merge_db_dir
# Generate the text reports (summary is sufficient).
report -out $cov_report_dir/cov_report.txt -summary -inst uvm_pkg $dut \
-metrics all -cumulative on -local off -grading covered
# Generate the HTML reports.
report_metrics -out $cov_report_dir -title $dut_uc -overwrite \
-detail -kind aggregate -metrics all -source on \
-exclComments -assertionStatus -allAssertionCounters \
-all -inst -extended true

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vendor/lowrisc_ip/dv/tools/xcelium/xcelium.mk vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Makefile option groups that can be enabled by test Makefile / command line.
# These are generic set of option groups that apply to all testbenches.
# Simulator too specific options
# Mandatory items to set (these are used by rules.mk):
# SIMCC - Simulator compiler used to build / elaborate the bench
# SIMX - Simulator executable used to run the tests
SIMCC := xrun -elaborate
SIMX ?= xrun
SIM_SETUP ?= ${MAKE_ROOT}/xcelium/xcelium.tcl
# max number of errors before the run is stopped
ERROR_MAX := 50
# set standard build options
BUILD_OPTS += -l ${BUILD_LOG}
BUILD_OPTS += -access +r
BUILD_OPTS += -messages
BUILD_OPTS += -errormax ${ERROR_MAX}
BUILD_OPTS += -sv
BUILD_OPTS += -timescale 1ns/1ps
BUILD_OPTS += -uvmhome ${UVM_HOME}
BUILD_OPTS += -xmlibdirname ${SV_FLIST_GEN_DIR}/xcelium.d
BUILD_OPTS += -f ${SV_FLIST}
BUILD_OPTS += -64bit
BUILD_OPTS += -xprop F # -xverbose << add to see which modules does not have xprop enabled
# set standard run options
RUN_OPTS += -input ${SIM_SETUP}
RUN_OPTS += +SVSEED=${SEED}
RUN_OPTS += +UVM_VERBOSITY=${UVM_VERBOSITY}
RUN_OPTS += +UVM_TESTNAME=${UVM_TEST}
RUN_OPTS += +UVM_TEST_SEQ=${UVM_TEST_SEQ}
RUN_OPTS += -l ${RUN_LOG}
RUN_OPTS += -xmlibdirname ${SV_FLIST_GEN_DIR}/xcelium.d -R
RUN_OPTS += -64bit
#########################
## Tool Specific Modes ##
#########################
# Enable simulation profiling
XCELIUM_SIMPROFILE ?= 0
ifeq (${XCELIUM_SIMPROFILE},1)
endif
# Enable coverage
XCELIUM_COV ?= 0
ifeq (${XCELIUM_COV},1)
endif

26
vendor/lowrisc_ip/dv/tools/xcelium/xcelium.tcl vendored Normal file
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# TCL file invoked from xcelium simulations at run-time using this: -input <this file>
# Get some environment variables we need.
set en_waves 0
set tool_srcs_dir ""
if {[info exists ::env(EN_WAVES)]} {
set en_waves "$::env(EN_WAVES)"
}
if {[info exists ::env(TOOL_SRCS_DIR)]} {
set tool_srcs_dir "$::env(TOOL_SRCS_DIR)"
} else {
puts "ERROR: tool script run without TOOL_SRCS_DIR environment variable."
quit
}
# If wave dumping is enabled, run waves.tcl
if {"$en_waves" == 1} {
source "${tool_srcs_dir}/waves.tcl"
}
run
quit

33
vendor/patches/lowrisc_ip/dv_data/0001-common-sim-cfg.patch vendored Normal file
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@ -0,0 +1,33 @@
--- a/common_sim_cfg.hjson
+++ b/common_sim_cfg.hjson
@@ -2,17 +2,13 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
- project: opentitan
- doc_server: docs.opentitan.org
- results_server: reports.opentitan.org
-
// Where to find DV code
- dv_root: "{proj_root}/hw/dv"
+ dv_root: "{proj_root}/vendor/lowrisc_ip/dv"
flow: sim
flow_makefile: "{dv_root}/data/sim.mk"
- import_cfgs: ["{proj_root}/hw/data/common_project_cfg.hjson",
+ import_cfgs: ["{proj_root}/dv/uvm/common_project_cfg.hjson",
"{dv_root}/data/common_modes.hjson",
"{dv_root}/data/fusesoc.hjson",
"{dv_root}/data/{tool}/{tool}.hjson"]
--- a/fusesoc.hjson
+++ b/fusesoc.hjson
@@ -10,7 +10,7 @@
"--target=sim",
"--build-root={build_dir}",
"--setup {fusesoc_core}"]
- fusesoc_cores_root_dirs: ["--cores-root {proj_root}/hw"]
+ fusesoc_cores_root_dirs: ["--cores-root {proj_root}"]
sv_flist_gen_dir: "{build_dir}/sim-vcs"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
}