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Clean Verilator warning about X-IF addition while keeping the RTL SEC-safe (#292)

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* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line

* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present

* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present

* [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF.
This commit is contained in:
Cairo Caplan 2025-04-08 21:29:25 +02:00 • committed by GitHub
parent 3bc12617f4
commit 6c47cd261b
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2 changed files with 4 additions and 4 deletions
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6
rtl/cve2_decoder.sv
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@ -210,7 +210,7 @@ module cve2_decoder #(
multdiv_operator_o = MD_OP_MULL;
multdiv_signed_mode_o = 2'b00;
rf_wdata_sel_o = RF_WD_EX;
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_EX});
rf_we = 1'b0;
rf_ren_a_o = 1'b0;
rf_ren_b_o = 1'b0;
@ -617,7 +617,7 @@ module cve2_decoder #(
end else begin
// instruction to read/modify CSR
csr_access_o = 1'b1;
rf_wdata_sel_o = RF_WD_CSR;
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_CSR});
rf_we = 1'b1;
if (~instr[14]) begin
@ -643,7 +643,7 @@ module cve2_decoder #(
rf_ren_a_o = x_issue_resp_register_read_i[0];
rf_ren_b_o = x_issue_resp_register_read_i[1];
rf_we = x_issue_resp_writeback_i;
rf_wdata_sel_o = RF_WD_COPROC;
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});
end
end

2
rtl/cve2_id_stage.sv
View file

@ -418,7 +418,7 @@ module cve2_id_stage #(
// Register file write data mux
always_comb begin : rf_wdata_id_mux
unique case (rf_wdata_sel)
unique case ($bits(rf_wd_sel_e)'({rf_wdata_sel}))
RF_WD_EX: rf_wdata_id_o = result_ex_i;
RF_WD_CSR: rf_wdata_id_o = csr_rdata_i;
RF_WD_COPROC: rf_wdata_id_o = XInterface? x_result_i.data : result_ex_i;