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update headers

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This commit is contained in:
Pasquale Davide Schiavone 2018-01-15 15:25:54 +01:00
parent d899348fe9
commit 71cb9878f4
19 changed files with 33 additions and 33 deletions
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14
zeroriscy_alu.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
@ -56,7 +56,7 @@ module zeroriscy_alu
begin : g_revloop
assign operand_a_rev[k] = operand_a_i[31-k];
end
endgenerate
endgenerate
/////////////////////////////////////
@ -68,7 +68,7 @@ module zeroriscy_alu
// //
/////////////////////////////////////
logic adder_op_b_negate;
logic adder_op_b_negate;
logic [32:0] adder_in_a, adder_in_b;
logic [31:0] adder_result;
@ -104,7 +104,7 @@ module zeroriscy_alu
assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
assign adder_result = adder_result_ext_o[32:1];
assign adder_result_o = adder_result;
////////////////////////////////////////
@ -188,7 +188,7 @@ module zeroriscy_alu
assign is_equal = (adder_result == 32'b0);
assign is_equal_result_o = is_equal;
// Is greater equal
always_comb
@ -199,7 +199,7 @@ module zeroriscy_alu
is_greater_equal = operand_a_i[31] ^ (cmp_signed);
end
// GTE unsigned:
// GTE unsigned:
// (a[31] == 1 && b[31] == 1) => adder_result[31] == 0
// (a[31] == 0 && b[31] == 0) => adder_result[31] == 0
// (a[31] == 1 && b[31] == 0) => 1
@ -277,5 +277,5 @@ module zeroriscy_alu
default: ; // default case to suppress unique warning
endcase
end
endmodule

2
zeroriscy_compressed_decoder.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_controller.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_core.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

8
zeroriscy_cs_registers.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
@ -148,7 +148,7 @@ module zeroriscy_cs_registers
////////////////////////////////////////////
// ____ ____ ____ ____ //
// / ___/ ___|| _ \ | _ \ ___ __ _ //
// | | \___ \| |_) | | |_) / _ \/ _` | //
// | | \___ \| |_) | | |_) / _ \/ _` | //
// | |___ ___) | _ < | _ < __/ (_| | //
// \____|____/|_| \_\ |_| \_\___|\__, | //
// |___/ //
@ -179,7 +179,7 @@ module zeroriscy_cs_registers
// mhartid: unique hardware thread id
12'hF14: csr_rdata_int = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
default: ;
endcase
end
@ -323,7 +323,7 @@ module zeroriscy_cs_registers
// assign external performance counters
generate
genvar i;
for (i = 0; i < N_EXT_CNT; i++)
for (i = 0; i < N_EXT_CNT; i++)
begin : g_extcounters
assign PCCR_in[N_PERF_COUNTERS - N_EXT_CNT + i] = ext_counters_i[i];
end

2
zeroriscy_debug_unit.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

4
zeroriscy_decoder.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
@ -220,7 +220,7 @@ module zeroriscy_decoder
alu_operator_o = ALU_ADD;
regfile_we = 1'b0;
end
end

2
zeroriscy_ex_block.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_fetch_fifo.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

4
zeroriscy_id_stage.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
@ -759,7 +759,7 @@ module zeroriscy_id_stage
// stall control
assign id_ready_o = (~load_stall) & (~branch_stall) & (~jump_stall) & (~multdiv_stall);
assign id_valid_o = (~halt_id) & id_ready_o;

2
zeroriscy_if_stage.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_int_controller.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

4
zeroriscy_load_store_unit.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
@ -410,7 +410,7 @@ module zeroriscy_load_store_unit
end
else begin
//if first part rvalid is NOT received
//the second grand is not received either by protocol.
//the second grand is not received either by protocol.
//stay here
NS = WAIT_RVALID_MIS;
end

2
zeroriscy_multdiv_fast.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_multdiv_slow.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

6
zeroriscy_prefetch_buffer.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
@ -149,7 +149,7 @@ module zeroriscy_prefetch_buffer
if (branch_i) begin
instr_addr_o = addr_i;
addr_valid = 1'b1;
end
end
if(instr_gnt_i)
NS = WAIT_RVALID;
@ -185,7 +185,7 @@ module zeroriscy_prefetch_buffer
if (branch_i) begin
addr_valid = 1'b1;
NS = WAIT_ABORTED;
end
end
end
end else begin
// just wait for rvalid and go back to IDLE, no new request

2
zeroriscy_register_file.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_register_file_ff.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at

2
zeroriscy_tracer.sv
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@ -1,4 +1,4 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at