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[DV] add support_unaligned_load_store setting (#521)

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Signed-off-by: Udi <udij@google.com>
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udinator 2019-12-13 13:44:18 -08:00 • committed by taoliug
parent f23b3f39fa
commit 8568e6b3b5
1 changed files with 3 additions and 0 deletions
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dv/uvm/riscv_dv_extension/riscv_core_setting.sv
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@ -31,6 +31,9 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE, USER_MODE};
// FENCE.I is intentionally treated as illegal instruction by ibex core
riscv_instr_name_t unsupported_instr[] = {FENCE_I};
// Specify whether processor supports unaligned loads and stores
bit support_unaligned_load_store = 1'b1;
// ISA supported by the processor
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};