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Fixes #110 : documentation updated accordingly

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Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
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Szymon Bieganski 2023-06-07 13:27:42 +02:00
parent b8c94a3e84
commit cf47f88e9e
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doc/02_user/integration.rst
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@ -133,7 +133,7 @@ Interfaces
| | | | from :ref:`csr-mhartid` CSR |
+----------------------------+-------------------------+-----+----------------------------------------+
| ``boot_addr_i`` | 32 | in | First program counter after reset |
| | | | = ``boot_addr_i`` + 0x80, |
| | | | = ``boot_addr_i``, |
| | | | see :ref:`exceptions-interrupts` |
+----------------------------+-------------------------+-----+----------------------------------------+
| ``instr_*`` | Instruction fetch interface, see :ref:`instruction-fetch` |

2
doc/03_reference/exception_interrupts.rst
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@ -14,7 +14,7 @@ The base address of the vector table is initialized to the boot address (must be
The base address can be changed after bootup by writing to the ``mtvec`` CSR.
For more information, see the :ref:`cs-registers` documentation.
The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte.
The core starts fetching at the address made by the most significant 3 bytes of the boot address.
It is assumed that the boot address is supplied via a register to avoid long paths to the instruction fetch unit.
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