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https://github.com/openhwgroup/cve2.git
synced 2025-04-23 13:37:20 -04:00
Fixed JAL/JALR instruction check, added pretty print function for invalid instructions
This commit is contained in:
Sven Stucki
parent
85d2632a38
commit
d7e8aba2f9
2 changed files with 60 additions and 54 deletions
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@ -303,13 +303,6 @@ module controller
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DECODE:
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begin
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// synopsys translate_off
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$display("%t: Decoding Instruction", $time);
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$display("%t: | fct7 | rs2 | rs1 | | rd | opc. |", $time);
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$display("%t: 0b %b %b %b %b %b %b", $time, instr_rdata_i[31:25], instr_rdata_i[`REG_RS2],
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instr_rdata_i[`REG_RS1], instr_rdata_i[14:12], instr_rdata_i[`REG_RD],
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instr_rdata_i[6:0]);
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// synopsys translate_on
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unique case (instr_rdata_i[6:0])
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//////////////////////////////////////
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@ -321,36 +314,30 @@ module controller
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//////////////////////////////////////
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`OPCODE_JAL: begin // Jump and Link
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if (instr_rdata_i inside `INSTR_JAL) begin
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pc_mux_sel_o = `PC_FROM_IMM;
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alu_pc_mux_sel_o = 1'b1;
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_C4;
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alu_operator = `ALU_ADD;
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regfile_alu_we = 1'b1;
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if (instr_rdata_i ==? `INSTR_JAL) begin
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pc_mux_sel_o = `PC_FROM_IMM;
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alu_pc_mux_sel_o = 1'b1;
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_C4;
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alu_operator = `ALU_ADD;
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regfile_alu_we = 1'b1;
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end else begin
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// synopsys translate_off
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$display("%t: Illegal JAL instruction: %b", $time, instr_rdata_i);
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// synopsys translate_on
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illegal_insn_o = 1'b1;
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illegal_insn_o = 1'b1;
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end
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end
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`OPCODE_JALR: begin // Jump and Link Register
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if (instr_rdata_i inside `INSTR_JALR) begin
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pc_mux_sel_o = `PC_FROM_REGFILE;
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_C4;
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alu_operator = `ALU_ADD;
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regfile_alu_we = 1'b1;
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rega_used = 1'b1;
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if (instr_rdata_i ==? `INSTR_JALR) begin
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pc_mux_sel_o = `PC_FROM_REGFILE;
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_C4;
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alu_operator = `ALU_ADD;
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regfile_alu_we = 1'b1;
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rega_used = 1'b1;
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end else begin
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// synopsys translate_off
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$display("%t: Illegal JALR instruction: %b", $time, instr_rdata_i);
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// synopsys translate_on
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illegal_insn_o = 1'b1;
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illegal_insn_o = 1'b1;
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end
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end
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@ -464,9 +451,6 @@ module controller
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`INSTR_SH: data_type_o = 2'b01;
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`INSTR_SB: data_type_o = 2'b10;
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default: begin
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// synopsys translate_off
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$display("%t: Illegal STORE instruction: %b", $time, instr_rdata_i);
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// synopsys translate_on
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data_req = 1'b0;
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data_we = 1'b0;
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rega_used = 1'b0;
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@ -503,9 +487,6 @@ module controller
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end
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default: begin
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// synopsys translate_off
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$display("%t: Illegal LOAD instruction: %b", $time, instr_rdata_i);
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// synopsys translate_on
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data_req = 1'b0;
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regfile_we = 1'b0;
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rega_used = 1'b0;
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@ -652,9 +633,6 @@ module controller
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`INSTR_SRLI: alu_operator = `ALU_SRL; // Shift Right Logical by Immediate
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`INSTR_SRAI: alu_operator = `ALU_SRA; // Shift Right Arithmetically by Immediate
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default: begin
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// synopsys translate_off
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$display("%t: Illegal OP-IMM instruction: %b", $time, instr_rdata_i);
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// synopsys translate_on
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regfile_alu_we = 1'b0;
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illegal_insn_o = 1'b1;
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end
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@ -1158,9 +1136,6 @@ module controller
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*/
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default: begin
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// synopsys translate_off
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$display("%t: Unknown Instruction 0x%h.", $time, instr_rdata_i[31:0]);
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// synopsys translate_on
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illegal_insn_o = 1'b1;
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// TODO: Replace with exception
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pc_mux_sel_o = `NO_INCR;
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@ -1168,8 +1143,12 @@ module controller
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endcase; // case (instr_rdata_i[6:0])
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if (illegal_insn_o = 1'b1) begin
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if (illegal_insn_o == 1'b1) begin
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// synopsys translate_off
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$display("%t: Illegal instruction:", $time, instr_rdata_i);
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prettyPrintInstruction(instr_rdata_i);
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$stop;
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// synopsys translate_on
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end
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// misaligned access was detected by the LSU
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@ -84,9 +84,6 @@
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`define OPCODE_SF 6'h39
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*/
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`define OPCODE_SYSTEM 7'h73
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`define OPCODE_FENCE 7'h0f
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`define OPCODE_OP 7'h33
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@ -147,12 +144,12 @@
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// SYSTEM
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`define INSTR_SCALL { {11 {1'b0}}, 1'b0, {13 {1'b0}}, `OPCODE_SYSTEM }
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`define INSTR_SBREAK { {11 {1'b0}}, 1'b1, {13 {1'b0}}, `OPCODE_SYSTEM }
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`define INSTR_RDCYCLE { 5'b11000, {5 {5'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDCYCLEH { 5'b11001, {5 {5'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDTIME { 5'b11000, {5 {5'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDTIMEH { 5'b11001, {5 {5'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDINSTRET { 5'b11000, {5 {5'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDINSTRETH { 5'b11001, {5 {5'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDCYCLE { 5'b11000, {5 {1'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDCYCLEH { 5'b11001, {5 {1'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDTIME { 5'b11000, {5 {1'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDTIMEH { 5'b11001, {5 {1'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDINSTRET { 5'b11000, {5 {1'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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`define INSTR_RDINSTRETH { 5'b11001, {5 {1'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM }
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// RV32M
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`define INSTR_MUL { 7'b0000001, {10 {1'b?}}, 3'b000, {5 {1'b?}}, `OPCODE_OP }
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@ -172,6 +169,36 @@
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`define REG_RD 11:07
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// synopsis translate off
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function void prettyPrintInstruction(input [31:0] instr);
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string opcode;
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begin
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unique case (instr[6:0])
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`OPCODE_SYSTEM: opcode = "SYSTEM";
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`OPCODE_FENCE: opcode = "FENCE";
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`OPCODE_OP: opcode = "OP";
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`OPCODE_OPIMM: opcode = "OPIMM";
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`OPCODE_STORE: opcode = "STORE";
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`OPCODE_LOAD: opcode = "LOAD";
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`OPCODE_BRANCH: opcode = "BRANCH";
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`OPCODE_JALR: opcode = "JALR";
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`OPCODE_JAL: opcode = "JAL";
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`OPCODE_AUIPC: opcode = "AUIPC";
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`OPCODE_LUI: opcode = "LUI";
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default: opcode = "Unknown";
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endcase // unique case (instr[6:0])
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$display("%t: %s Instruction 0x%h.", $time, opcode, instr[31:0]);
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$display("%t: | fct7 | rs2 | rs1 | | rd | opc. |", $time);
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$display("%t: 0b %b %b %b %b %b %b", $time, instr[31:25], instr[`REG_RS2],
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instr[`REG_RS1], instr[14:12], instr[`REG_RD], instr[6:0]);
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$display();
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end
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endfunction // prettyPrintInstruction
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// synopsis translate on
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//////////////////////////////////////////////////////////////////////////////
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// _ _ _ _ ___ _ _ //
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// / \ | | | | | | / _ \ _ __ ___ _ __ __ _| |_(_) ___ _ __ ___ //
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