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Fix issue #1 on github, byte address should always be 0

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This commit is contained in:
Andreas Traber 2016-04-26 16:56:42 +02:00
parent 101ef713f1
commit df014ec3ba
1 changed files with 6 additions and 2 deletions
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8
if_stage.sv
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@ -160,7 +160,7 @@ module riscv_if_stage
.req_i ( req_i ),
.branch_i ( branch_req ),
.addr_i ( fetch_addr_n ),
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),
.hwloop_i ( hwlp_jump ),
.hwloop_target_i ( hwlp_target ),
@ -191,7 +191,7 @@ module riscv_if_stage
.req_i ( 1'b1 ),
.branch_i ( branch_req ),
.addr_i ( fetch_addr_n ),
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),
.hwloop_i ( hwlp_jump ),
.hwloop_target_i ( hwlp_target ),
@ -382,4 +382,8 @@ module riscv_if_stage
assert property (
@(posedge clk) (instr_gnt_i) |-> (instr_req_o) );
// make sure LSB of fetch_addr_n is always 0
assert property (
@(posedge clk) (req_i) |-> (~fetch_addr_n[0]) );
endmodule