mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-22 21:17:59 -04:00
Move riscv-formal code into formal/riscv-formal
This leaves a space in the naming hierarchy for other formal tooling, like the Yosys flow I'm working on.
This commit is contained in:
parent
40a52ab8b4
commit
e4dbe46597
2 changed files with 3 additions and 3 deletions
|
@ -29,8 +29,8 @@ It should not be necessary to create the Verilog source manually as it is used b
|
|||
Run the following command from the top level directory of Ibex to create the Verilog source.
|
||||
|
||||
```console
|
||||
make -C formal
|
||||
make -C formal/riscv-formal
|
||||
```
|
||||
|
||||
This will create a directory *formal/build* which contains an equivalent Verilog file for each SystemVerilog source.
|
||||
The single output file *formal/ibex.v* contains the complete Ibex source, which can then be imported by riscv-formal.
|
||||
This will create a directory *formal/riscv-formal/build* which contains an equivalent Verilog file for each SystemVerilog source.
|
||||
The single output file *formal/riscv-formal/ibex.v* contains the complete Ibex source, which can then be imported by riscv-formal.
|
Loading…
Add table
Add a link
Reference in a new issue