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More warnings fixed

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This commit is contained in:
Sven Stucki 2015-07-23 02:30:44 +02:00
parent da7c740870
commit f908f34fcf
3 changed files with 3 additions and 6 deletions
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1
if_stage.sv
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@ -49,7 +49,6 @@ module if_stage
output logic [31:0] instr_addr_o, // address for instruction fetch
// Forwarding ports - control signals
input logic compressed_instr_i, // ID decoded a compressed instruction
input logic force_nop_i, // insert a NOP in the pipe
input logic [31:0] exception_pc_reg_i, // address used to restore the program counter when the interrupt/exception is served
input logic [31:0] pc_from_hwloop_i, // pc from hwloop start addr

2
riscv_core.sv
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@ -287,8 +287,6 @@ module riscv_core
.branch_decision_i ( branch_decision ),
.jump_target_i ( jump_target ),
.compressed_instr_i ( compressed_instr ),
// pipeline stalls
.stall_if_i ( stall_if ),
.stall_id_i ( stall_id )

6
wb_stage.sv
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@ -56,9 +56,9 @@ module wb_stage
always_comb
begin : REGFILE_WDATA_MUX
case (regfile_wdata_mux_sel_i)
//1'b0: regfile_wdata_o <= sp_rdata_i;
1'b1: regfile_wdata_o <= data_rdata_i;
default: regfile_wdata_o <= data_rdata_i;
//1'b0: regfile_wdata_o = sp_rdata_i;
1'b1: regfile_wdata_o = data_rdata_i;
default: regfile_wdata_o = data_rdata_i;
endcase; // case (regfile_wdata_mux_sel_i)
end