* Core-V eXtension Interface (CV-X-IF) integration (#277)
* minor fixes (#283)
* minor fix again
* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line (#289)
* Fix remaining sec inconsistency regarding the X-IF addition (#291)
* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line
* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* Clean Verilator warning about X-IF addition while keeping the RTL SEC-safe (#292)
* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line
* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF.
* fix xif
---------
Co-authored-by: FrancescoDeMalde-synthara <167969440+FrancescoDeMalde-synthara@users.noreply.github.com>
Co-authored-by: Cairo Caplan <cairo.caplan@eclipse-foundation.org>
* [rtl] Changed the default number of performance counters from 0 to 10 (#214)
* Implementation of sequential equivalence checking option using Yosys EQY.
* [sec] Automatic removal of new IO when performing SEC against (current) golden design with Yosys EQY
