Commit graph

Select branches

Hide pull requests

main

x_if

#1

#102

#11

#111

#112

#113

#114

#115

#116

#118

#119

#120

#120

#122

#123

#124

#125

#126

#127

#127

#129

#131

#132

#133

#134

#138

#139

#141

#143

#144

#145

#148

#149

#149

#150

#152

#154

#155

#156

#157

#158

#158

#16

#160

#167

#167

#170

#174

#174

#178

#18

#180

#181

#181

#182

#182

#183

#183

#184

#19

#20

#23

#24

#25

#26

#266

#27

#270

#272

#273

#273

#275

#276

#277

#278

#279

#279

#282

#283

#284

#285

#286

#287

#288

#289

#29

#290

#291

#292

#47

#48

#49

#50

#51

#52

#55

#56

#95

#96

#97

#98

#99

Mono Color

• 7000ef2594
  Merge 1372bdc95f into 468b3595cd Christian Herber 2025-04-17 19:10:37 +00:00
• d5d57a2119
  Merge beefd93d5b into 468b3595cd szbieg 2025-04-17 12:38:50 +02:00
• abad1f6a72
  Merge ee822c878f into 468b3595cd szbieg 2025-04-16 16:06:58 +00:00
• 1f96e0d3b2
  Merge 8fb1fce9ad into 468b3595cd Lee Hoff 2025-04-14 13:59:34 +00:00
• d649700c01
  Merge e022a3091c into 468b3595cd Daniele Parravicini 2025-04-13 21:13:33 +00:00
• ac753fff98
  Merge 7f81ba7738 into 468b3595cd Cairo Caplan 2025-04-10 14:15:04 +02:00
• 468b3595cd
  add X-IF 1.0 (#284) main Davide Schiavone 2025-04-10 14:06:34 +02:00
• 7071272fe1 fix xif x_if davide schiavone 2025-04-10 10:49:03 +02:00
• 6c47cd261b
  Clean Verilator warning about X-IF addition while keeping the RTL SEC-safe (#292) Cairo Caplan 2025-04-08 21:29:25 +02:00
• d7cea56723
  Merge cf47f88e9e into 44393eb863 szbieg 2025-03-27 12:01:05 +00:00
• 9c424deeb7 [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF. Cairo Caplan 2025-03-26 10:31:51 +01:00
• 926c378220
  Merge branch 'openhwgroup:x_if' into x_if Cairo Caplan 2025-03-25 10:10:52 +01:00
• 3bc12617f4
  Fix remaining sec inconsistency regarding the X-IF addition (#291) Cairo Caplan 2025-03-25 09:27:12 +01:00
• 7e076079db [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present Cairo Caplan 2025-03-24 16:56:01 +01:00
• 6cc6d3d055 [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present Cairo Caplan 2025-03-24 16:56:01 +01:00
• 0d52b7dbeb
  Merge branch 'openhwgroup:x_if' into x_if Cairo Caplan 2025-03-24 16:25:03 +01:00
• 1ef01050dd fix rf_we davide schiavone 2025-03-17 16:41:22 +01:00
• e8e7967079
  Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line (#289) Cairo Caplan 2025-03-17 14:57:02 +01:00
• 076d6f95f2 Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line Cairo Caplan 2025-03-17 13:33:37 +01:00
• 7f81ba7738
  Merge branch 'openhwgroup:main' into main Cairo Caplan 2025-03-17 11:15:06 +01:00
• 73ba22204f merge main davide schiavone 2025-03-17 11:06:35 +01:00
• 44393eb863
  Logical Equivalence Checking with Yosys EQY (#287) Cairo Caplan 2025-03-17 10:49:24 +01:00
• 7d9c17da51
  Merge branch 'openhwgroup:main' into lec_yosys Cairo Caplan 2025-03-17 09:42:56 +01:00
• 7472bc1ce3
  Modification debug interface output halted status (#288) Luis Waucquez 2025-03-14 17:01:09 +01:00
• 2d2f36aba5
  Merge branch 'openhwgroup:main' into main Cairo Caplan 2025-03-13 09:27:24 +01:00
• 1af825d9a1
  Merge a38bc25cab into ca6bc061a2 szbieg 2025-03-11 13:48:31 -07:00
• 0142dfbdfc
  Merge 1ae4209022 into ca6bc061a2 Davide Schiavone 2025-03-11 13:48:31 -07:00
• fe71c0a1f5
  Merge 1c6f55dcc5 into ca6bc061a2 szbieg 2025-03-11 13:48:31 -07:00
• 636ccafdb7
  Merge 6eb09e79a1 into ca6bc061a2 szbieg 2025-03-11 13:48:31 -07:00
• ca6bc061a2
  Add content about the ECA/MCCA. Mike Thompson 2025-03-11 16:30:20 -04:00
• 25878916c3 Modification debug interface output halted status Luis Donatien 2025-03-11 16:06:49 +01:00
• 750bad2f58 [sec] Automatic removal of new IO when performing SEC against (current) golden design with Yosys EQY Cairo Caplan 2025-03-07 19:41:28 +01:00
• b7e0af5b46
  Merge branch 'openhwgroup:main' into lec_yosys Cairo Caplan 2025-03-07 18:57:25 +01:00
• d18d25efbe
  Merge branch 'openhwgroup:main' into main Cairo Caplan 2025-03-05 18:15:24 +01:00
• dc64df4047 Implementation of sequential equivalence checking option using Yosys EQY. Cairo Caplan 2025-03-05 18:03:54 +01:00
• 9df7ab1bab
  Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286) Cairo Caplan 2025-03-03 16:56:26 +01:00
• c480b5781c Adding buildsim.log to .gitignore, as it is created by some make targets Cairo Caplan 2025-02-28 17:42:13 +01:00
• 3341779e74 [doc] Updating the docs regarding the turning of debug halt and exception addresses into signals (#269) Cairo Caplan 2025-02-28 17:41:43 +01:00
• 8fafa71814 [rtl] Turning debug halt and exception addresses from parameters into signals (#269) Cairo Caplan 2025-02-28 17:41:24 +01:00
• 2814470132 minor fix again davide schiavone 2025-02-27 19:34:31 +01:00
• b74beda8f1 minor fix again davide schiavone 2025-02-27 19:34:31 +01:00
• 9046348e29
  minor fixes (#283) Davide Schiavone 2025-02-27 14:37:10 +01:00
• 76247da60d minor fixes davide schiavone 2025-02-27 14:30:51 +01:00
• 4cd1a8ddc2
  Core-V eXtension Interface (CV-X-IF) integration (#277) FrancescoDeMalde-synthara 2025-02-27 14:28:23 +01:00
• 61df50c304 minor cleaning and fixes davide schiavone 2025-02-27 14:26:04 +01:00
• a86d1b2828 [rtl] Changed the default number of performance counters from 0 to 10 (#214) Cairo Caplan 2025-02-17 16:11:09 +01:00
• b7e5534480
  Update marchid, mvendorid, mimpid values in docs (#278) Mohammed Eladawy 2025-02-05 19:13:33 +02:00
• ad15d5a1c3
  Update getting_started.rst Davide Schiavone 2025-02-05 18:13:08 +01:00
• f4747b3a03 Update marchid, mvendorid, mimpid values in docs Mohammed Eladawy 2025-02-01 23:12:17 +02:00
• 1c879966d9 CV-X-IF disabled by default Francesco De Maldè 2025-01-29 12:37:50 +01:00
• 840763b467 The offloading of instructions through the CV-X-IF is now not dependent on the opcode Francesco De Maldè 2025-01-29 11:51:35 +01:00
• 90f1205b4f Core-V eXtension Interface (CV-X-IF) integration Francesco De Maldè 2025-01-28 10:18:21 +01:00
• 4b782ac0d7
  Hot fix for pr_trigger workflow Mike Thompson 2025-01-14 16:49:31 -05:00
• 8640594d0d
  Adding the proper Reset-Value and detailed table to the MISA in the UM (#276) Ahmed Eid 2025-01-14 22:57:54 +02:00
• 8ba4e39931 Removing RVB Comment AhmedEid0199 2025-01-14 21:57:49 +02:00
• 2f3a19cdfa Replace Hardcoded Values with Parameters AhmedEid0199 2025-01-14 20:21:44 +02:00
• a946c23596 Adding detailed table to MISA register in the CV32E20 UM AhmedEid0199 2025-01-14 04:34:39 +02:00
• 5daea96181 Adding Reset-value and detailed table to MISA register in the CV32E20 UM AhmedEid0199 2025-01-14 04:29:42 +02:00
• 64ab9282ae Add XIF signals fmme26 2024-11-01 14:34:36 +01:00
• 1ad765947a feat: add xif signals fmme26 2024-10-28 13:15:07 +01:00
• 370793f524
  RVFI CSRs improvements (#266) MarioOpenHWGroup 2024-06-19 14:02:12 +02:00
• e022a3091c Replace Ibex with CV32E20 in doc indices DanieleParravicini-Synthara 2024-06-13 14:52:52 +02:00
• f40ce9cea9 Fixes Entry0 of interrupt vector table DanieleParravicini-Synthara 2024-06-13 14:52:43 +02:00
• 2a9f3c669a Add interrupt vector table description DanieleParravicini-Synthara 2024-06-10 09:27:06 +02:00
• e315edd234 Update cve2 docs about boot_addr_i DanieleParravicini-Synthara 2024-06-10 09:26:56 +02:00
• 65d53a7cd6 Add comment on cve2_controller about irq_fast DanieleParravicini-Synthara 2024-06-10 09:26:42 +02:00
• 067341d4e1
  Delete commented lines Mario 2024-06-06 10:45:52 +00:00
• cd43ee5dbf adding back obi2ahbm example Davide Schiavone 2024-06-06 11:38:53 +02:00
• c6609445c2
  Add RVFI debug signals Mario 2024-06-05 17:08:41 +00:00
• 42f76f433c
  Remove the Ibex example system (#272) Mike Thompson 2024-05-28 18:23:18 +00:00
• c763e093ca Remove the Ibex example system mike 2024-05-28 12:13:17 -04:00
• 7f3bb9fcb2
  fix design compiler (#270) Davide Schiavone 2024-05-27 15:23:26 +02:00
• 014a4ccb73 fix design compiler davide schiavone 2024-05-27 14:38:42 +02:00
• 07a55ced92
  Add rvfi_interface binded to the cve2_core Mario 2024-05-23 10:35:54 +00:00
• a502dd5d96
  RVFI CSRs improvements Mario 2024-05-17 12:38:28 +00:00
• 1786fbfab7
  add RVFI CSRs tracing (#184) MarioOpenHWGroup 2024-02-26 13:05:23 +01:00
• ed08230f73
  Change cve2_pkg import on cs_registers Mario 2024-02-26 11:57:43 +00:00
• 00bad9703a
  Do not count dret instruction when not in debug mode - it won't retire (#180) szbieg 2024-02-26 12:30:02 +01:00
• 6b81da3653
  Add RVFI CSRs tracing Mario 2024-02-22 14:16:35 +00:00
• 8a561eddcf
  HotFix: need the latest version of Sphinx Mike Thompson 2024-01-30 10:26:13 -05:00
• beefd93d5b
  [rtl] restore read/write logic for CSR_CPUCTRL solves #177 Szymon Bieganski 2024-01-24 13:47:04 +01:00
• 6eb09e79a1
  Remove SECURESEED csr Solves #96 Szymon Bieganski 2024-01-10 13:36:59 +01:00
• ebddc3938f
  Merge pull request #148 from NXP/feature/specification-improvements christian-herber-nxp 2023-12-21 20:07:21 +01:00
• 8fb1fce9ad updating obi2ahb gasket document Lee Hoff 2023-12-21 10:30:20 -05:00
• 21ba59ced7
  Do not count dret instruction when not in debug mode - it won't retire fixes #164 Szymon Bieganski 2023-12-20 11:07:49 +01:00
• f5b21e71c9
  removed unused irq_enable signal in controller (#178) Davide Schiavone 2023-12-12 13:40:59 +01:00
• ee822c878f
  [rtl] expose effective priv_mode along with non-translated one Szymon Bieganski 2023-12-12 13:38:03 +01:00
• d62922f226 removed unused irq_enable signal in controller davide schiavone 2023-12-12 13:25:09 +01:00
• 13c86e6a0a
  adding obi2ahb gasket (#160) Lee Hoff 2023-12-12 02:31:46 -05:00
• 3243c43f8b updating obi2ahb gasket Lee Hoff 2023-12-11 16:10:19 -05:00
• e74a5f616a
  [rtl] use Machine/User mode encoding as per RVpriv specification the the exposed signals closes #175 Szymon Bieganski 2023-12-04 09:35:44 +01:00
• e6f07ccde7
  [doc] encode the the exposed op-mode directly, without any conversion Szymon Bieganski 2023-12-01 14:55:34 +01:00
• d858331a88
  Merge branch 'openhwgroup:main' into feature/expmmode szbieg 2023-12-01 14:33:11 +01:00
• 1372bdc95f
  [doc] list additional CSRs Szymon Bieganski 2023-11-22 14:11:27 +01:00
• f05cdd90b7
  [doc] correct typo Szymon Bieganski 2023-11-20 12:23:31 +01:00
• ad54ed05d5
  [doc] refer to the original Ibex implementation Szymon Bieganski 2023-11-15 12:16:41 +01:00
• fd2ff1897a
  Merge pull request #170 from davideschiavone/main christian-herber-nxp 2023-11-14 09:13:25 -06:00
• 315621bd15
  [doc] reference to the specification draft/documentation Szymon Bieganski 2023-11-14 13:25:37 +01:00
• e58f0593c3
  Merge pull request #1 from davideschiavone/davideschiavone-fixreadme Davide Schiavone 2023-11-14 10:22:44 +01:00
• a325e5ebba
  add references and fix typos in README Davide Schiavone 2023-11-14 10:20:20 +01:00