mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-20 03:57:25 -04:00
* rename files and modules to cve2 Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * updated tb files Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remaining references to ibex: gitignore, examples, etc. Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
25 lines
605 B
Text
25 lines
605 B
Text
CAPI=2:
|
|
# Copyright lowRISC contributors.
|
|
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
name: "lowrisc:cve2:sim_shared"
|
|
description: "Collection of useful RTL for building simulations"
|
|
filesets:
|
|
files_sim_sv:
|
|
depend:
|
|
- lowrisc:prim:assert
|
|
- lowrisc:prim:ram_1p
|
|
- lowrisc:prim:ram_2p
|
|
files:
|
|
- ./rtl/ram_1p.sv
|
|
- ./rtl/ram_2p.sv
|
|
- ./rtl/bus.sv
|
|
- ./rtl/sim/simulator_ctrl.sv
|
|
- ./rtl/timer.sv
|
|
file_type: systemVerilogSource
|
|
|
|
targets:
|
|
default:
|
|
filesets:
|
|
- files_sim_sv
|
|
|