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https://github.com/openhwgroup/cve2.git
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932db14619
* rename files and modules to cve2 Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * updated tb files Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remaining references to ibex: gitignore, examples, etc. Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
62 lines
2.5 KiB
Tcl
62 lines
2.5 KiB
Tcl
# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# List of inputs and outputs. Number is timing constraint expressed as a % of
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# clock cycle, e.g.
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#
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# {instr_req_o 70.0}
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#
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# as an output means the instr_req_o output must be stable by 60% of total clock
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# cycle
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#
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# {instr_gnt_i 30.0}
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#
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# as an input means the instr_gnt_i input will be stable by 30% of the total
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# clock cycle
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# These IO constraints are an educated guess, they effectively assume there's a
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# bit of external logic on the inputs and outputs but not much before they reach
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# a flop.
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set lr_synth_outputs [list {instr_req_o 70.0} \
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{instr_addr_o 70.0} \
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{data_req_o 70.0} \
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{data_we_o 70.0} \
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{data_be_o 70.0} \
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{data_addr_o 70.0} \
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{data_wdata_o 70.0} \
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{core_sleep_o 80.0}]
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set lr_synth_inputs [list {test_en_i 0.0 } \
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{hart_id_i 0.0 } \
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{boot_addr_i 0.0 } \
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{instr_gnt_i 30.0} \
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{instr_rvalid_i 30.0} \
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{instr_rdata_i 30.0} \
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{instr_err_i 30.0} \
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{data_gnt_i 30.0} \
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{data_rvalid_i 30.0} \
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{data_rdata_i 30.0} \
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{data_err_i 30.0} \
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{irq_software_i 10.0} \
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{irq_timer_i 10.0} \
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{irq_external_i 10.0} \
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{irq_fast_i 10.0} \
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{irq_nm_i 10.0} \
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{debug_req_i 10.0} \
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{fetch_enable_i 0.0 }]
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# clock and reset IO names (at top-level)
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set lr_synth_clk_input clk_i
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set lr_synth_rst_input rst_ni
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# clock period in ps, this gives a 250 MHz clock. using the nangate45 library
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# Ibex can happily meet this on all paths with the lr_synth_abc_clk_uprate
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# setting below. With a lower uprate timing may not be met.
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set lr_synth_clk_period 4000.0
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# Amount to subtract from clk period to give the clock period passed to ABC in
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# the synth flow. ABC maps the design to the standard cell library and
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# optimises paths for timing, better results are obtained by giving it a faster
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# clock period so it optimises more.
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set lr_synth_abc_clk_uprate 2000.0
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