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cve2/shared/rtl/fpga/xilinx
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Canberk Topal 1b1247e1de [fpga] Changed to 2p_ram for FPGA top level 
1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2021-08-03 16:51:16 +01:00
..
clkgen_xil7series.sv [fpga] Changed to 2p_ram for FPGA top level 2021-08-03 16:51:16 +01:00