cve2/shared/rtl
christian-herber-nxp 932db14619
Rename all modules to cve2 (#25)
* rename files and modules to cve2

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* updated tb files

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remaining references to ibex: gitignore, examples, etc.

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
2023-01-05 10:27:24 +01:00
..
fpga/xilinx [fpga] Changed to 2p_ram for FPGA top level 2021-08-03 16:51:16 +01:00
sim Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
bus.sv
ram_1p.sv
ram_2p.sv
timer.sv