Pirmin Vogel 16d6f5ea2b [rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0 ... This invovles the following changes: - Rename pcnt to cpop - Switch encoding of max and minu - Remove rev from Balanced version, only available in Full version via grev (Zbp) - Include sext.b/h (previously in Zb_tmp) - Remove slo[i] and sro[i] from Balanced version, only available in Full version (Zbp) Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>		2021-12-03 22:43:05 +01:00
..
ibex_alu.sv	[rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0	2021-12-03 22:43:05 +01:00
ibex_branch_predict.sv	Fix Xcelium warnings	2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_controller.sv	[rtl] RVFI changes and extensions for co-simulation	2021-10-15 11:30:35 +01:00
ibex_core.f	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
ibex_core.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_counter.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00
ibex_cs_registers.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00
ibex_csr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_decoder.sv	[rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0	2021-12-03 22:43:05 +01:00
ibex_dummy_instr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_ex_block.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_fetch_fifo.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_icache.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_id_stage.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_if_stage.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_load_store_unit.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_lockstep.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_multdiv_fast.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_multdiv_slow.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_pkg.sv	[rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0	2021-12-03 22:43:05 +01:00
ibex_pmp.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_prefetch_buffer.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_register_file_ff.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_register_file_fpga.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_register_file_latch.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_top.sv	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
ibex_top_tracing.sv	[rtl] RVFI changes and extensions for co-simulation	2021-10-15 11:30:35 +01:00
ibex_tracer.sv	[rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0	2021-12-03 22:43:05 +01:00
ibex_tracer_pkg.sv	[rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0	2021-12-03 22:43:05 +01:00
ibex_wb_stage.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00