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3a42f12e64
This commit was prepared by the following script, followed by manual
fixes as needed.
```sh
sed -e 's/zeroriscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zero-riscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zeroriscy/ibex/g' -i.bak include/*.sv
sed -e 's/zero-riscy/ibex/g' -i.bak include/*.sv
sed -e 's/cluster_clock_gating/clock_gating/g' -i.bak *.sv
rm -f *.bak
rm -f include/*.bak
find . -name 'zeroriscy_*' -exec bash -c 'file={}; git mv $file ${file/zeroriscy/ibex}' \;
```
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ibex: RISC-V Core
ibex is a small 2-stage RISC-V core derived from RI5CY.
ibex fully implements the RV32IMC instruction set and a minimal set of RISCV privileged specifications. ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions. This configuration is called micro-riscy
The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the control core for PULP and PULPino.
Documentation
A datasheet that explains the most important features of the core can be found in the doc folder.