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95 lines
6 KiB
ReStructuredText
95 lines
6 KiB
ReStructuredText
.. _exceptions-interrupts:
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Exceptions and Interrupts
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=========================
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Ibex implements trap handling for interrupts and exceptions according to the RISC-V Privileged Specification, version 1.11.
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All exceptions cause the core to jump to the base address of the vector table in the ``mtvec`` CSR.
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Interrupts are handled in vectored mode, i.e., the core jumps to the base address plus four times the interrupt ID.
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The base address of the vector table is given by the boot address (must be aligned to 256 bytes, i.e., its least significant byte must be 0x00).
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The most significant 3 bytes of the boot address given to the core are used for the first instruction fetch of the core and as the basis of the interrupt vector table.
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The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte.
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The boot address can be changed after the first instruction was fetched to change the interrupt vector table address.
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It is assumed that the boot address is supplied via a register to avoid long paths to the instruction fetch unit.
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Interrupts
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----------
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Ibex supports the following interrupts.
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+-------------------------+-------+--------------------------------------------------+
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| Interrupt Input Signal | ID | Description |
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+=========================+=======+==================================================+
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| ``irq_nm_i`` | 31 | Non-maskable interrupt (NMI) |
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+-------------------------+-------+--------------------------------------------------+
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| ``irq_fast_i[14:0]`` | 30:16 | 15 fast, local interrupts |
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+-------------------------+-------+--------------------------------------------------+
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| ``irq_external_i`` | 11 | Connected to platform-level interrupt controller |
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+-------------------------+-------+--------------------------------------------------+
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| ``irq_timer_i`` | 7 | Connected to timer module |
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+-------------------------+-------+--------------------------------------------------+
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| ``irq_software_i`` | 3 | Connected to memory-mapped (inter-processor) |
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| | | interrupt register |
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+-------------------------+-------+--------------------------------------------------+
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All interrupts except for the non-maskable interrupt (NMI) are controlled via the ``mstatus``, ``mie`` and ``mip`` CSRs.
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After reset, all interrupts are disabled.
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To enable interrupts, both the global interrupt enable (MIE) bit in the ``mstatus`` CSR and the corresponding individual interrupt enable bit in the ``mie`` CSR need to be set.
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For more information, see the :ref:`cs-registers` documentation.
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If multiple interrupts are pending, the highest priority is given to the interrupt with the highest ID.
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The NMI is enabled independent of the values in the ``mstatus`` and ``mie`` CSRs, and it is not visible through the ``mip`` CSR.
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It has interrupt ID 31, i.e., it has the highest priority of all interrupts and the core jumps to the trap-handler base address (in ``mtvec``) plus 0x7C to handle the NMI.
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All interrupt lines are level-sensitive.
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It is assumed that the interrupt handler signals completion of the handling routine to the interrupt source, e.g., through a memory-mapped register, which then deasserts the corresponding interrupt line.
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In debug mode, all interrupts including the NMI are ignored independent of ``mstatus``.MIE and the content of the ``mie`` CSR.
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Recoverable Non-Maskable Interrupt
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----------------------------------
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To support recovering from an NMI happening during a trap handling routine, Ibex features additional CSRs for backing up ``mstatus``.MPP, ``mstatus``.MPIE, ``mepc`` and ``mcause``.
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These CSRs are not accessible by software running on the core.
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These CSRs are nonstandard.
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For more information, see `the corresponding proposal <https://github.com/riscv/riscv-isa-manual/issues/261>`_.
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Exceptions
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----------
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Ibex can trigger an exception due to the following exception causes:
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+----------------+---------------------------------------------------------------+
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| Exception Code | Description |
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+----------------+---------------------------------------------------------------+
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| 2 | Illegal instruction |
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+----------------+---------------------------------------------------------------+
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| 3 | Breakpoint |
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+----------------+---------------------------------------------------------------+
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| 5 | Load access fault |
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+----------------+---------------------------------------------------------------+
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| 7 | Store access fault |
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+----------------+---------------------------------------------------------------+
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| 11 | Environment call from M-mode (ECALL) |
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+----------------+---------------------------------------------------------------+
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The illegal instruction exception, LSU error exceptions and ECALL instruction exceptions cannot be disabled and are always active.
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Handling
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--------
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Ibex does support nested interrupt/exception handling.
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Exceptions inside interrupt/exception handlers cause another exception.
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However, exceptions during the critical part of your exception handlers, i.e. before having saved the ``mepc`` and ``mstatus``, will cause those CSRs to be overwritten.
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Interrupts during interrupt/exception handlers are thus disabled by default, but can be explicitly enabled if desired.
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When entering an interrupt/exception handler, the core sets ``mepc`` to the current program counter and saves ``mstatus``.MIE to ``mstatus``.MPIE.
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Upon executing an MRET instruction, the core jumps to the program counter saved in the ``mepc`` CSR and restores ``mstatus``.MPIE to ``mstatus``.MIE.
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