github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-24 14:09:08 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
cve2/examples
History
Rahul Behl 76ac3ef658 Updates to the sim timescale option 
- Updated the timescale option to not include "=" in between the
    timescale directive and the value passed. See #181 for further
    details
2019-07-29 16:00:35 +01:00
..
fpga/artya7-100 Adapt interrupt IF for Arty example, tracer and TB 2019-07-24 18:58:26 +01:00
sim Updates to the sim timescale option 2019-07-29 16:00:35 +01:00
sw/led Ibex example Arty A7-100T 2019-07-11 16:09:49 +01:00