6ce8b6ecf2
Update code from upstream repository https://github.com/google/riscv- dv to revision 4b333ba1ef285ec4508c606efa64610136154a5e * cg instantion based on supported_isa (google/riscv-dv#303) (udinator) * Fix coverage collection issue, change default target to rv32imc (google/riscv-dv#302) (taoliug) * Integrate whisper(swerv-ISS) (google/riscv-dv#301) (taoliug) * Fix cov.py, set UVM_VERBOSITY to UVM_HIGH for verbose mode (google/riscv-dv#299) (taoliug) * Fix jalr handling issue for ovpsim (google/riscv-dv#298) (taoliug) * Add noclean option, change default output directory of coverage collection (google/riscv-dv#297) (taoliug) * Enable using core trace logs for coverage collection (google/riscv- dv#291) (udinator) * Fix isa/mabi setup issue for RV64GC target (google/riscv-dv#296) (taoliug) * fixed line widths (x2) and check error returns for any questa simalator (google/riscv-dv#293) (simond-imperas) * Unknown instruction fix (google/riscv-dv#290) (simond-imperas) * Fix ovpsim log process issue (google/riscv-dv#289) (udinator) * adding riscvOVPsim vector instruction trace to csv processing - start (3rd Attempt) (google/riscv-dv#288) (simond-imperas) Signed-off-by: Udi <udij@google.com> |
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| CONTRIBUTING.md | ||
| CREDITS.md | ||
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| LICENSE | ||
| README.md | ||
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Ibex RISC-V Core
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.
This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.