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91eb8564de
* [rtl] Flush controller in PMP CSR write ops As Greg pointed out: When we have an instruction in ID/EX that writes a PMP register that update gets written to the CSR the same cycle the next instruction moves from IF to ID/EX with it's PMP check done with the old value. The solution is to flush the pipeline when we get a PMP CSR write. Signed-off-by: Canberk Topal <ctopal@lowrisc.org> * [rtl] Flush pipe on MSECCFG CSR write Without this an instruction executed immediately after the MSECCFG write doesn't have the new MSECCFG setup applied to its execute permission. --------- Signed-off-by: Canberk Topal <ctopal@lowrisc.org> Co-authored-by: Canberk Topal <ctopal@lowrisc.org> Co-authored-by: Greg Chadwick <gac@lowrisc.org> |
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| .. | ||
| cve2_alu.sv | ||
| cve2_branch_predict.sv | ||
| cve2_compressed_decoder.sv | ||
| cve2_controller.sv | ||
| cve2_core.f | ||
| cve2_core.sv | ||
| cve2_counter.sv | ||
| cve2_cs_registers.sv | ||
| cve2_csr.sv | ||
| cve2_decoder.sv | ||
| cve2_ex_block.sv | ||
| cve2_fetch_fifo.sv | ||
| cve2_id_stage.sv | ||
| cve2_if_stage.sv | ||
| cve2_load_store_unit.sv | ||
| cve2_multdiv_fast.sv | ||
| cve2_multdiv_slow.sv | ||
| cve2_pkg.sv | ||
| cve2_pmp.sv | ||
| cve2_pmp_reset_default.svh | ||
| cve2_prefetch_buffer.sv | ||
| cve2_register_file_ff.sv | ||
| cve2_register_file_fpga.sv | ||
| cve2_register_file_latch.sv | ||
| cve2_top.sv | ||
| cve2_top_tracing.sv | ||
| cve2_tracer.sv | ||
| cve2_tracer_pkg.sv | ||
| cve2_wb_stage.sv | ||