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Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d * [flash] updated flash wrapper md file (Dana Agur) * [flash / top / ast] functional updates (Timothy Chen) * [ralgen, dv] Associated changes to ralgen (Srikrishna Iyer) * [prim_sync_reqack_data] Fix SVA checking DST-to-SRC data stability (Pirmin Vogel) * [dv/keymgr] temp disable alert checking in scb (Cindy Chen) * [dvsim] Fix a wrong path in print message (Weicai Yang) * [prim] Teach verilator to recognise a clock gate (Rupert Swarbrick) * [prim_lc_sync] Add AsyncOn parameter to enable/disable the sync flops (Michael Schaffner) * [clkmgr / top] Add clock divider step down to support lc_ctrl transition (Timothy Chen) * [prim_sync_reqack] Use NRZ protocol internally for increased throughput (Pirmin Vogel) * [prim] correct interface documentation. (Timothy Chen) * [flash_ctrl] Add tlul configuration interface to prim_flash (Timothy Chen) * [flash_ctrl] Use hamming code for 64b ECC (Timothy Chen) * [prim/edn] Fix lint error (width mismatch) (Eunchan Kim) Signed-off-by: Greg Chadwick <gac@lowrisc.org> |
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eembc_coremark | ||
google_riscv-dv | ||
lowrisc_ip | ||
patches | ||
eembc_coremark.lock.hjson | ||
google_riscv-dv.lock.hjson | ||
google_riscv-dv.vendor.hjson | ||
lowrisc_ip.lock.hjson | ||
lowrisc_ip.vendor.hjson |