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Previous lint fix was incorrect. The 'always_comb' block here should be an 'always'. It is not combinational logic but rather an infinite loop to generate a clock when running in a simulator that isn't verilator (e.g. under simple-system under VCS) so the use of 'always' is appropriate. Signed-off-by: Greg Chadwick <gac@lowrisc.org> |
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fpga/artya7 | ||
simple_system | ||
sw |