Greg Chadwick 58bc6f27ab [doc] Add details about icache latency to DIT docs ... When the icache is enabled and data independent timing is required variable fetch latency due to cache hit or miss may introduce undesirable timing behaviour. This adds explicit mention of this to the documentation.		2022-02-23 08:48:12 +00:00
..
images	[doc] Add new Ibex testplan	2022-01-11 12:49:04 +00:00
cosim.rst	Refer to a specific tag for the ibex-cosim version of Spike	2022-02-21 09:43:11 +00:00
coverage_plan.rst	[dv] Add initial coverage plan	2022-01-06 13:47:04 +00:00
cs_registers.rst	[rtl,doc] Add double fault detection.	2022-01-25 15:05:39 +00:00
debug.rst	Add support for additional HW breakpoints	2020-10-19 13:20:08 +02:00
exception_interrupts.rst	[rtl,doc] Add double fault detection.	2022-01-25 15:05:39 +00:00
history.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
icache.rst	[doc] Fix inline literal syntax in icache.rst	2022-02-02 10:19:13 +00:00
index.rst	[doc] Add new Ibex testplan	2022-01-11 12:49:04 +00:00
instruction_decode_execute.rst	[bitmanip, doc] Update info on bitmanip support and area numbers	2021-12-16 14:18:00 +01:00
instruction_fetch.rst	[rtl] Add bus integrity checking	2021-08-26 16:55:26 +01:00
load_store_unit.rst	[secded] Switch to inverted ECC codes	2021-12-02 15:14:11 -08:00
performance_counters.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
pipeline_details.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
pmp.rst	[rtl,doc] Add customisable PMP reset values	2022-01-24 10:01:36 +00:00
register_file.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
rvfi.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
security.rst	[doc] Add details about icache latency to DIT docs	2022-02-23 08:48:12 +00:00
testplan.rst	[doc] Add new Ibex testplan	2022-01-11 12:49:04 +00:00
tracer.rst	[rtl] Add a new top level plus wiring	2021-04-07 12:07:38 +01:00
verification.rst	[docs] Update description of ISS versions	2022-02-16 12:26:36 +00:00