cve2/rtl
Tom Roberts 12b39476c0 [rtl] Add speculative branch signal
- Drive a speculative version of the branch signal into the IF stage to
  drive address muxing
- The speculative signal is the same as the regular branch signal but
  assumes all conditional branches are taken
- This breaks the timing path from branch condition calculation into
  address muxing (and therefore PMP error calculation)
- When the branch is not taken, any external request we might otherwise
  have made is suppressed
- This has a minor performance cost (0.8% without I$, ~0% with I$)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-05-26 09:41:37 +01:00
..
ibex_alu.sv [bitmanip] Add ZBR instruction group 2020-05-22 17:21:03 +02:00
ibex_compressed_decoder.sv [rtl] Introduce default clk/reset to prim_assert 2020-02-10 09:42:52 +00:00
ibex_controller.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_core.f Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr 2020-03-06 12:49:51 +01:00
ibex_core.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_core_tracing.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_counters.sv Use a syntax compatible with Verible 2020-03-13 10:34:12 +00:00
ibex_cs_registers.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_decoder.sv [bitmanip] Add ZBR instruction group 2020-05-22 17:21:03 +02:00
ibex_dummy_instr.sv [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
ibex_ex_block.sv [rtl] Add data-independent timing to multdiv_fast 2020-05-15 10:19:55 +01:00
ibex_fetch_fifo.sv [rtl] Prevent xprop from fetch fifo 2020-05-26 09:33:50 +01:00
ibex_icache.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_id_stage.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_if_stage.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_load_store_unit.sv [assertions] Tweak xprop assertion qualifiers 2020-05-26 09:33:50 +01:00
ibex_multdiv_fast.sv [rtl] Add data-independent timing to multdiv_fast 2020-05-15 10:19:55 +01:00
ibex_multdiv_slow.sv [rtl] data-independent execution for multdiv_slow 2020-05-15 10:19:55 +01:00
ibex_pkg.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_pmp.sv [rtl] Fix PMP address matching 2020-05-26 09:33:50 +01:00
ibex_prefetch_buffer.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_register_file_ff.sv [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
ibex_register_file_fpga.sv [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
ibex_register_file_latch.sv [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
ibex_tracer.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_tracer_pkg.sv [bitmanip] Add ZBR instruction group 2020-05-22 17:21:03 +02:00
ibex_wb_stage.sv [RTL] Add configurable third pipeline stage 2020-03-06 15:29:14 +00:00