mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-24 14:09:08 -04:00
9d976c7ab7
ram_1p is almost a copy of the single-port RAM primitive we have in OpenTitan, called prim_ram_1p, with its generic implementation prim_generic_ram_1p. Instead of having a copy of that file in Ibex, consistently use the OpenTitan one. Unfortunately, ram_1p has slightly different semantics around some signals, especially rvalid. This commit adjusts the meanings of the signals for now, since I don't have a way to test the Arty board which also uses this primitive (together with the compliance test suite). With the testing in the compliance suite I'm reasonably certain that the Arty board will work as well. |
||
|---|---|---|
| .. | ||
| rtl | ||
| fpga_xilinx.core | ||
| prim_assert.core | ||
| prim_generic_ram_1p.core | ||
| prim_lfsr.core | ||
| prim_ram_1p.core | ||
| prim_secded.core | ||
| sim_shared.core | ||