Include assert macros when they are used

prim_assert.sv is a file containing assertion macros (defines).
Previously, prim_assert.sv was compiled as normal SystemVerilog file.
This made the defines available for the whole compilation unit as soon
as they were defined. Since all cores using prim_assert depended (in
fusesoc) on the lowrisc:prim:assert core, prim_assert was always
compiled first, and the defines were visible in subsequent files.

All of that is only true if all files end up in one comilation unit. The
SV standard states that what makes up a compilation unit is
tool-defined, but also states that typically, passing multiple files (or
a file list/.f file) to a single tool invocation means that all files
end up in one compilation unit; if the tool is called multiple times,
then the files end up in separate compilation units.

Edalize (the fusesoc backend) doesn't guarantee either behavior, and so
it happens that for Vivado, Verilator, Cadence and Synopsys simulators,
all files are compiled into a single compilation unit. But for Riviera,
each file is a separate compilation unit.

To avoid relying on the definition of compilation units, and to do the
generally right thing (TM), this commit changes the code to always
include the prim_assert.sv file when it is used in a source file.
Include guards are introduced in the prim_assert.sv file to avoid
defining things twice.

lint/verilator_waiver.vlt

@@ -25,7 +25,7 @@ lint_off -msg UNUSED -file "*/rtl/ibex_if_stage.sv" -lines 40
 
 // Bits of signal are not used: fetch_addr_n[0]
 // cleaner to write all bits even if not all are used
-lint_off -msg UNUSED -file "*/rtl/ibex_if_stage.sv" -lines 80
+lint_off -msg UNUSED -file "*/rtl/ibex_if_stage.sv" -lines 83
 
 // Bits of signal are not used: shift_right_result_ext[32]
 // cleaner to write all bits even if not all are used
@@ -33,15 +33,15 @@ lint_off -msg UNUSED -file "*/rtl/ibex_alu.sv" -lines 104
 
 // Bits of signal are not used: alu_adder_ext_i[0]
 // Bottom bit is round, not needed
-lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 23
+lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 26
 
 // Bits of signal are not used: mac_res_ext[34]
 // cleaner to write all bits even if not all are used
-lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 48
+lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 51
 
 // Bits of signal are not used: res_adder_h[32]
 // cleaner to write all bits even if not all are used
-lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 68
+lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 71
 
 // Signal is not used: test_en_i
 // testability signal
@@ -51,17 +51,17 @@ lint_off -msg UNUSED -file "*/rtl/ibex_register_file_fpga.sv" -lines 22
 // Signal is not used: clk_i
 // leaving clk and reset connected in-case we want to add assertions
 lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 15
-lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 14
-lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 21
+lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 17
+lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 24
 
 // Signal is not used: rst_ni
 // leaving clk and reset connected in-case we want to add assertions
-lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 16
-lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 15
-lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 22
+lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 19
+lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 18
+lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 25
 lint_off -msg UNUSED -file "*/rtl/ibex_register_file_fpga.sv" -lines 20
 
 // Signal unoptimizable: Feedback to clock or circular logic:
 // ibex_core.cs_registers_i.mie_q
 // Issue lowrisc/ibex#212
-lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 167
+lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 170

rtl/ibex_compressed_decoder.sv

@@ -10,6 +10,9 @@
  * This module is fully combinatorial, clock and reset are used for
  * assertions only.
  */
+
+`include "prim_assert.sv"
+
 module ibex_compressed_decoder (
     input  logic        clk_i,
     input  logic        rst_ni,

rtl/ibex_controller.sv

@@ -6,6 +6,9 @@
 /**
  * Main controller of the processor
  */
+
+`include "prim_assert.sv"
+
 module ibex_controller (
     input  logic                  clk_i,
     input  logic                  rst_ni,

rtl/ibex_cs_registers.sv

@@ -9,6 +9,9 @@
  * Control and Status Registers (CSRs) following the RISC-V Privileged
  * Specification, draft version 1.11
  */
+
+`include "prim_assert.sv"
+
 module ibex_cs_registers #(
     parameter bit          DbgTriggerEn     = 0,
     parameter int unsigned MHPMCounterNum   = 8,

rtl/ibex_decoder.sv

@@ -14,6 +14,9 @@
  * This module is fully combinatorial, clock and reset are used for
  * assertions only.
  */
+
+`include "prim_assert.sv"
+
 module ibex_decoder #(
     parameter bit RV32E = 0,
     parameter bit RV32M = 1

rtl/ibex_fetch_fifo.sv

@@ -9,6 +9,9 @@
  * input port: send address and data to the FIFO
  * clear_i clears the FIFO for the following cycle, including any new request
  */
+
+`include "prim_assert.sv"
+
 module ibex_fetch_fifo #(
   parameter int unsigned NUM_REQS = 2
 ) (

rtl/ibex_id_stage.sv

@@ -13,6 +13,9 @@
  * Decode stage of the core. It decodes the instructions and hosts the register
  * file.
  */
+
+`include "prim_assert.sv"
+
 module ibex_id_stage #(
     parameter bit RV32E = 0,
     parameter bit RV32M = 1

rtl/ibex_if_stage.sv

@@ -9,6 +9,9 @@
  * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of
  * the read instruction.
  */
+
+`include "prim_assert.sv"
+
 module ibex_if_stage #(
     parameter int unsigned DmHaltAddr      = 32'h1A110800,
     parameter int unsigned DmExceptionAddr = 32'h1A110808

rtl/ibex_load_store_unit.sv

@@ -9,6 +9,9 @@
  * Load Store Unit, used to eliminate multiple access during processor stalls,
  * and to align bytes and halfwords.
  */
+
+`include "prim_assert.sv"
+
 module ibex_load_store_unit (
     input  logic         clk_i,
     input  logic         rst_ni,

rtl/ibex_multdiv_fast.sv

@@ -11,6 +11,9 @@
  *
  * 16x16 kernel multiplier and Long Division
  */
+
+`include "prim_assert.sv"
+
 module ibex_multdiv_fast (
     input  logic             clk_i,
     input  logic             rst_ni,

rtl/ibex_multdiv_slow.sv

@@ -8,6 +8,9 @@
  *
  * Baugh-Wooley multiplier and Long Division
  */
+
+`include "prim_assert.sv"
+
 module ibex_multdiv_slow (
     input  logic             clk_i,
     input  logic             rst_ni,

shared/prim_assert.core

@@ -8,7 +8,7 @@ description: "Assertion primitives"
 filesets:
   files_rtl:
     files:
-      - rtl/prim_assert.sv
+      - rtl/prim_assert.sv : {is_include_file : true}
     file_type: systemVerilogSource
 
 targets:

shared/rtl/prim_assert.sv

@@ -6,6 +6,9 @@
 //  - Provides default clk and rst options to simplify code
 //  - Provides boiler plate template for common assertions
 
+`ifndef PRIM_ASSERT_SV
+`define PRIM_ASSERT_SV
+
 `ifdef UVM
   // report assertion error with UVM if compiled
   package assert_rpt_pkg;
@@ -172,3 +175,5 @@
 `ifdef FPV_ON                                    \
    `COVER(__name, __prop, __clk, __rst)          \
 `endif
+
+`endif // PRIM_ASSERT_SV

shared/rtl/timer.sv

@@ -3,6 +3,9 @@
 // SPDX-License-Identifier: Apache-2.0
 
 // Example memory mapped timer
+
+`include "prim_assert.sv"
+
 module timer #(
   // Bus data width (must be 32)
   parameter int unsigned DataWidth    = 32,