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06f50ddeac
This commit fixes three possible cases for erroneous generation of
illegal instruction signals. Also, the bit-slices considered for
decoding ALU instructions are corrected to better reflect their
encoding specifications.
* Fix decoding of orc_b in illegal_insn generation.
* Insn[31] is no longer checked for generation of illegal instructions:
This bit is part of the rs3 register adress for ternary
bitmanipulation instructions (zbt).
* Correct bit-slicing for ALU reg-immediate instructions according
to specification: immediates are encoded in the range
insn[26:20] in all cases. Where a shift-amount is encoded, bits
[26:25] will have no effect, but will no longer generate
illegal instructions.
Signed-off-by: ganoam <gnoam@live.com>
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| .. | ||
| ibex_alu.sv | ||
| ibex_compressed_decoder.sv | ||
| ibex_controller.sv | ||
| ibex_core.f | ||
| ibex_core.sv | ||
| ibex_core_tracing.sv | ||
| ibex_counters.sv | ||
| ibex_cs_registers.sv | ||
| ibex_decoder.sv | ||
| ibex_ex_block.sv | ||
| ibex_fetch_fifo.sv | ||
| ibex_icache.sv | ||
| ibex_id_stage.sv | ||
| ibex_if_stage.sv | ||
| ibex_load_store_unit.sv | ||
| ibex_multdiv_fast.sv | ||
| ibex_multdiv_slow.sv | ||
| ibex_pkg.sv | ||
| ibex_pmp.sv | ||
| ibex_prefetch_buffer.sv | ||
| ibex_register_file_ff.sv | ||
| ibex_register_file_fpga.sv | ||
| ibex_register_file_latch.sv | ||
| ibex_tracer.sv | ||
| ibex_tracer_pkg.sv | ||
| ibex_wb_stage.sv | ||