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Pirmin Vogel 0778008f33 [rtl] Remove X assignments, add SVAs for selector signals 
This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2019-12-20 10:09:09 +01:00
..
verilator_waiver.vlt [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00