github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-24 14:09:08 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
1312 commits 2 branches 0 tags 14 MiB
Find a file
Tom Roberts e45e314686 [verilator] Separate out memory loading utilities 
- Split memory utils out of VerilatorSimCtrl
- Allows VerilatorSimCtrl to be used in systems not requiring memory loading
- Fixes #317
2019-12-23 21:35:30 +01:00
doc [doc] Add a comment on mhpmcounter optimization 2019-12-11 15:02:29 +00:00
dv [verilator] Separate out memory loading utilities 2019-12-23 21:35:30 +01:00
examples [examples] Fix spelling for description type 2019-12-04 13:59:46 +00:00
lint [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
rtl [rtl] By default, forward incoming instruction in C decoder 2019-12-20 10:09:09 +01:00
shared [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
syn [syn] Add initial Yosys synthesis script with example lib 2019-11-29 17:03:44 +00:00
vendor Update google_riscv-dv to google/riscv-dv@9ecee87 (#530) 2019-12-18 10:46:36 -08:00
.clang-format Add lowRISC standard clang-format file 2019-09-11 12:00:49 +01:00
.gitignore Update gitignore to include simple system files 2019-11-25 14:13:17 +01:00
azure-pipelines.yml [ci] Add CS registers TB to CI 2019-12-03 15:38:56 +00:00
CONTRIBUTING.md Fix vim setting suggestion 2019-06-19 14:39:41 +02:00
CREDITS.md Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
ibex_core.core [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
ibex_core_tracing.core [dv] Remove clock gating primitive in dv/uvm/tb 2019-11-16 00:25:32 +01:00
ibex_tracer.core [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
LICENSE Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
Makefile [make] Fix target reference 2019-12-21 10:05:39 +01:00
README.md Add link to CREDITS.md from README.md 2019-08-27 18:10:02 +01:00
src_files.yml [RTL] - Add PMP module 2019-08-29 17:43:37 +01:00

README.md

Build Status

Ibex RISC-V Core

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Documentation

The Ibex user manual can be read online at ReadTheDocs. It is also contained in the doc folder of this repository.

Contributing

We highly appreciate community contributions. To ease our work of reviewing your contributions, please:

  • Create your own branch to commit your changes and then open a Pull Request.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages. For more information, please check out the contribution guide.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.

To get started, please check out the "Good First Issue" list.

Issues and Troubleshooting

If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.

Questions?

Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Credits

Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.

References

  1. Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)