cve2/shared
Pirmin Vogel 0778008f33 [rtl] Remove X assignments, add SVAs for selector signals
This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2019-12-20 10:09:09 +01:00
..
rtl [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
fpga_xilinx.core Use shared code for Arty A7-100T example 2019-11-14 13:20:19 +01:00
prim_assert.core [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
sim_shared.core Added simple system 2019-11-09 07:48:47 +00:00