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Adjusted test cases for new GPIO base address

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This commit is contained in:
David Harris 2022-01-26 19:15:48 +00:00
parent c6adb7b6b1
commit 0023c4cb57
5 changed files with 5 additions and 5 deletions
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2
tests/testsBP/fpga-blink-led/blink-led.s
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@ -47,7 +47,7 @@ _start:
# write to gpio # write to gpio
li x2, 0xFF li x2, 0xFF
la x3, 0x10012000 la x3, 0x10060000
# +8 is output enable # +8 is output enable
# +C is output value # +C is output value

2
tests/testsBP/fpga-test-dram/blink-led.s
View file

@ -47,7 +47,7 @@ _start:
# write to gpio # write to gpio
li x2, 0xFF li x2, 0xFF
la x3, 0x10012000 la x3, 0x10060000
# +8 is output enable # +8 is output enable
# +C is output value # +C is output value

2
tests/testsBP/fpga-test-sdc/old.asm
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@ -71,7 +71,7 @@ copy_sdc2:
# write to gpio # write to gpio
li x2, 0xFF li x2, 0xFF
la x3, 0x10012000 la x3, 0x10060000
# +8 is output enable # +8 is output enable
# +C is output value # +C is output value

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
View file

@ -27,7 +27,7 @@
#define RAM_RANGE 0x7FFFFFFF #define RAM_RANGE 0x7FFFFFFF
#define CLINT_BASE 0x02000000 #define CLINT_BASE 0x02000000
#define CLINT_RANGE 0x0000FFFF #define CLINT_RANGE 0x0000FFFF
#define GPIO_BASE 0x10012000 #define GPIO_BASE 0x10060000
#define GPIO_RANGE 0x000000FF #define GPIO_RANGE 0x000000FF
#define UART_BASE 0x10000000 #define UART_BASE 0x10000000
#define UART_RANGE 0x00000007 #define UART_RANGE 0x00000007

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S
View file

@ -27,7 +27,7 @@
#define RAM_RANGE 0x7FFFFFFF #define RAM_RANGE 0x7FFFFFFF
#define CLINT_BASE 0x02000000 #define CLINT_BASE 0x02000000
#define CLINT_RANGE 0x0000FFFF #define CLINT_RANGE 0x0000FFFF
#define GPIO_BASE 0x10012000 #define GPIO_BASE 0x10060000
#define GPIO_RANGE 0x000000FF #define GPIO_RANGE 0x000000FF
#define UART_BASE 0x10000000 #define UART_BASE 0x10000000
#define UART_RANGE 0x00000007 #define UART_RANGE 0x00000007