mirror of
https://github.com/openhwgroup/cvw.git
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Made the fpga top level configurable between rvvi synth and not.
This commit is contained in:
Rose Thompson
parent
9471dcd296
commit
00840e4893
2 changed files with 108 additions and 142 deletions
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@ -21,60 +21,22 @@ set_property port_width 32 [get_debug_ports u_ila_0/probe0]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][0]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][1]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][2]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][3]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][4]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][5]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][6]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][7]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][8]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][9]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][10]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][11]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][12]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][13]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][14]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][15]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][16]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][17]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][18]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][19]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][20]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][21]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][22]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][23]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][24]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][25]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][26]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][27]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][28]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][29]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][30]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][31]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe1]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list RvviAxiWlast ]]
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connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe2]
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set_property port_width 64 [get_debug_ports u_ila_0/probe2]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
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connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe3]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list {RvviAxiRlast}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe4]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list {RvviAxiRvalid}]]
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create_debug_port u_ila_0 probe
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set_property port_width 4 [get_debug_ports u_ila_0/probe5]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list {packetizer/CurrState[0]} {packetizer/CurrState[1]} {packetizer/CurrState[2]} {packetizer/CurrState[3]}]]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe6]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe7]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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connect_debug_port u_ila_0/probe7 [get_nets [list {RvviAxiWvalid}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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connect_debug_port u_ila_0/probe8 [get_nets [list {RVVIStall}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe9]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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connect_debug_port u_ila_0/probe9 [get_nets [list {valid}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe10]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
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connect_debug_port u_ila_0/probe10 [get_nets [list {RvviAxiWready}]]
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create_debug_port u_ila_0 probe
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set_property port_width 3 [get_debug_ports u_ila_0/probe11]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
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connect_debug_port u_ila_0/probe11 [get_nets [list {triggergen/CurrState[0]} {triggergen/CurrState[1]} {triggergen/CurrState[2]}]]
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connect_debug_port u_ila_0/probe3 [get_nets [list {RVVIStall}]]
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# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
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@ -78,7 +78,7 @@ module fpgaTop
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wire CPUCLK;
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wire c0_ddr4_ui_clk_sync_rst;
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(* mark_debug = "true" *) wire bus_struct_reset;
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wire bus_struct_reset;
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wire peripheral_reset;
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wire interconnect_aresetn;
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wire peripheral_aresetn;
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@ -1114,109 +1114,110 @@ module fpgaTop
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.init_calib_complete(c0_init_calib_complete),
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.device_temp(device_temp));
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localparam MAX_CSRS = 3;
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localparam TOTAL_CSRS = 36;
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// pipeline controlls
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logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
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// required
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logic [P.XLEN-1:0] PCM;
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logic InstrValidM;
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logic [31:0] InstrRawD;
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logic [63:0] Mcycle, Minstret;
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logic TrapM;
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logic [1:0] PrivilegeModeW;
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// registers gpr and fpr
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logic GPRWen, FPRWen;
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logic [4:0] GPRAddr, FPRAddr;
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logic [P.XLEN-1:0] GPRValue, FPRValue;
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logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
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(* mark_debug = "true" *) logic valid;
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logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
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if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
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localparam MAX_CSRS = 3;
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localparam TOTAL_CSRS = 36;
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// pipeline controlls
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logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
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// required
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logic [P.XLEN-1:0] PCM;
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logic InstrValidM;
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logic [31:0] InstrRawD;
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logic [63:0] Mcycle, Minstret;
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logic TrapM;
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logic [1:0] PrivilegeModeW;
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// registers gpr and fpr
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logic GPRWen, FPRWen;
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logic [4:0] GPRAddr, FPRAddr;
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logic [P.XLEN-1:0] GPRValue, FPRValue;
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logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
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assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
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assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
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assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
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assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE;
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assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM;
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assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW;
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assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
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assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
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assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
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assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM;
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assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
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assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
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assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
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assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
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assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
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assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
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assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
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logic valid;
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logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
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assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
|
||||
assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
|
||||
assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
|
||||
assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
|
||||
assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
|
||||
assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
|
||||
assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE;
|
||||
assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM;
|
||||
assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW;
|
||||
assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
|
||||
assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
|
||||
assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
|
||||
assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
|
||||
assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||
assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM;
|
||||
assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
|
||||
assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
|
||||
assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
|
||||
assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
|
||||
assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
|
||||
assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
|
||||
assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
|
||||
|
||||
rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
|
||||
.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
|
||||
.valid, .rvvi);
|
||||
assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
|
||||
assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
|
||||
assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
|
||||
assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
|
||||
assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
|
||||
assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
|
||||
assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
|
||||
assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
|
||||
assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
|
||||
assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
|
||||
assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
|
||||
assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
|
||||
assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
|
||||
assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
|
||||
assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
|
||||
assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
|
||||
assign CSRArray[16] = 0; // 12'hF11
|
||||
assign CSRArray[17] = 0; // 12'hF12
|
||||
assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
|
||||
assign CSRArray[19] = 0; // 12'hF15
|
||||
assign CSRArray[20] = 0; // 12'h34A
|
||||
// supervisor CSRs
|
||||
assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
|
||||
assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
|
||||
assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
|
||||
assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
|
||||
assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
|
||||
assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
|
||||
assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
|
||||
assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
|
||||
assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
|
||||
assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
|
||||
assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
|
||||
assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
|
||||
// user CSRs
|
||||
assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
|
||||
assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
|
||||
assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
|
||||
|
||||
// axi 4 write data channel
|
||||
(* mark_debug = "true" *) logic [31:0] RvviAxiWdata;
|
||||
(* mark_debug = "true" *) logic [3:0] RvviAxiWstrb;
|
||||
(* mark_debug = "true" *) logic RvviAxiWlast;
|
||||
(* mark_debug = "true" *) logic RvviAxiWvalid;
|
||||
(* mark_debug = "true" *) logic RvviAxiWready;
|
||||
rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
|
||||
.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
|
||||
.valid, .rvvi);
|
||||
|
||||
(* mark_debug = "true" *) logic [31:0] RvviAxiRdata;
|
||||
logic [3:0] RvviAxiRstrb;
|
||||
(* mark_debug = "true" *) logic RvviAxiRlast;
|
||||
(* mark_debug = "true" *) logic RvviAxiRvalid;
|
||||
(* mark_debug = "true" *) logic IlaTrigger;
|
||||
|
||||
// axi 4 write data channel
|
||||
logic [31:0] RvviAxiWdata;
|
||||
logic [3:0] RvviAxiWstrb;
|
||||
logic RvviAxiWlast;
|
||||
logic RvviAxiWvalid;
|
||||
logic RvviAxiWready;
|
||||
|
||||
logic [31:0] RvviAxiRdata;
|
||||
logic [3:0] RvviAxiRstrb;
|
||||
logic RvviAxiRlast;
|
||||
logic RvviAxiRvalid;
|
||||
(* mark_debug = "true" *) logic IlaTrigger;
|
||||
|
||||
|
||||
|
||||
logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
|
||||
logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
|
||||
logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
|
||||
logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
|
||||
|
||||
packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
|
||||
.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
|
||||
|
|
@ -1242,8 +1243,11 @@ module fpgaTop
|
|||
.cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
triggergen triggergen(.clk(CPUCLK), .reset(bus_struct_reset), .RvviAxiRdata,
|
||||
.RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger);
|
||||
triggergen triggergen(.clk(CPUCLK), .reset(bus_struct_reset), .RvviAxiRdata,
|
||||
.RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger);
|
||||
end else begin // if (P.RVVI_SYNTH_SUPPORTED)
|
||||
assign RVVIStall = '0;
|
||||
end
|
||||
|
||||
//assign phy_reset_n = ~bus_struct_reset;
|
||||
assign phy_reset_n = ~1'b0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue