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fix testbench

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Jordan Carlin 2024-11-16 12:53:10 -08:00
parent f6b0805fd4
commit 00d02e5656
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testbench/testbench.sv
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@ -564,7 +564,7 @@ module testbench;
assign SPIIn = 1'b0;
if(P.EXT_MEM_SUPPORTED) begin
ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE))
ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
end else begin