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https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Busybear: next week of updates
- move parsed instructions out of git, to /courses/e190ax/busybear_boot - parsed first 1M instructions, and now parse from split GDB runs - now at about 230k instructions, can't progress further for now since atomic instructions aren't implemented yet
This commit is contained in:
Noah Boorstin
parent
52ffb617d9
commit
01b1b1705d
2 changed files with 44 additions and 34 deletions
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@ -138,6 +138,5 @@ add wave /testbench_busybear/InstrWName
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run 1483850
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#run -all
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run -all
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##quit
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@ -47,59 +47,59 @@ module testbench_busybear();
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// read pc trace file
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integer data_file_PC, scan_file_PC;
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initial begin
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data_file_PC = $fopen("../busybear-testgen/parsedPC.txt", "r");
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data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
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if (data_file_PC == 0) begin
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$display("file couldn't be opened");
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$stop;
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#10; $stop;
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end
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end
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integer data_file_PCW, scan_file_PCW;
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initial begin
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data_file_PCW = $fopen("../busybear-testgen/parsedPC.txt", "r");
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data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
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if (data_file_PCW == 0) begin
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$display("file couldn't be opened");
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$stop;
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#10; $stop;
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end
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end
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// read register trace file
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integer data_file_rf, scan_file_rf;
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initial begin
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data_file_rf = $fopen("../busybear-testgen/parsedRegs.txt", "r");
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data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r");
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if (data_file_rf == 0) begin
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$display("file couldn't be opened");
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$stop;
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#10; $stop;
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end
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end
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// read CSR trace file
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integer data_file_csr, scan_file_csr;
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initial begin
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data_file_csr = $fopen("../busybear-testgen/parsedCSRs.txt", "r");
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data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r");
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if (data_file_csr == 0) begin
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$display("file couldn't be opened");
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$stop;
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#10; $stop;
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end
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end
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// read memreads trace file
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integer data_file_memR, scan_file_memR;
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initial begin
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data_file_memR = $fopen("../busybear-testgen/parsedMemRead.txt", "r");
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data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r");
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if (data_file_memR == 0) begin
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$display("file couldn't be opened");
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$stop;
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#10; $stop;
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end
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end
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// read memwrite trace file
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integer data_file_memW, scan_file_memW;
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initial begin
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data_file_memW = $fopen("../busybear-testgen/parsedMemWrite.txt", "r");
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data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r");
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if (data_file_memW == 0) begin
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$display("file couldn't be opened");
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$stop;
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#10; $stop;
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end
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end
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@ -115,6 +115,7 @@ module testbench_busybear();
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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#10; $stop;
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end
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end else begin
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scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
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@ -124,6 +125,7 @@ module testbench_busybear();
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end
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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#10; $stop;
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end
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end
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end
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@ -136,13 +138,14 @@ module testbench_busybear();
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if (dut.MemRWM[1]) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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$stop;
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#10; $stop;
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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#1;
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if (HADDR != readAdrExpected) begin
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$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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#10; $stop;
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end
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end
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end
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@ -154,15 +157,17 @@ module testbench_busybear();
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if (HWRITE) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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$stop;
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#10; $stop;
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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if (writeDataExpected != HWDATA) begin
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$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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#10; $stop;
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end
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if (writeAdrExpected != HADDR) begin
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$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
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#10; $stop;
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end
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end
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end
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@ -194,12 +199,14 @@ module testbench_busybear();
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end \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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#10; $stop; \
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end \
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end else begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(`"CSR`")) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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#10; $stop; \
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end \
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end \
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end \
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@ -235,10 +242,10 @@ module testbench_busybear();
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if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin
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if($feof(data_file_PCW)) begin
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$display("no more PC data to read");
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$stop;
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#10; $stop;
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end
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scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW);
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if (PCtextW != "ret") begin
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if (PCtextW != "ret" && PCtextW != "fence" && PCtextW != "nop" && PCtextW != "mret") begin
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scan_file_PC = $fscanf(data_file_PCW, "%s\n", PCtext2W);
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PCtextW = {PCtextW, " ", PCtext2W};
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end
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@ -247,6 +254,7 @@ module testbench_busybear();
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
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if(dut.ifu.PCW != PCWExpected) begin
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$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected);
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#10; $stop;
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end
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//if(it.InstrW != InstrWExpected) begin
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// $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
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@ -270,11 +278,11 @@ module testbench_busybear();
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//if (~speculative) begin
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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$stop;
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#10; $stop;
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end
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
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if (PCtext != "ret") begin
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if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret") begin
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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PCtext = {PCtext, " ", PCtext2};
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end
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@ -287,23 +295,26 @@ module testbench_busybear();
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
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(instrs <= 100000 && instrs % 10000 == 0)) begin
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(instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
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$display("loaded %0d instructions", instrs);
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end
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instrs += 1;
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// are we at a branch/jump?
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casex (lastInstrF[15:0])
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16'bXXXXXXXXX1101111, // JAL
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16'bXXXXXXXXX1100111, // JALR
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16'bXXXXXXXXX1100011, // B
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16'b110XXXXXXXXXXX01, // C.BEQZ
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16'b111XXXXXXXXXXX01, // C.BNEZ
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16'b101XXXXXXXXXXX01: // C.J
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casex (lastInstrF[31:0])
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32'b00000000001000000000000001110011, // URET
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32'b00010000001000000000000001110011, // SRET
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32'b00110000001000000000000001110011, // MRET
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
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32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
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32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
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32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
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speculative = 1;
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16'b1001000000000010: // C.EBREAK:
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32'bXXXXXXXXXXXXXXXX1001000000000010: // C.EBREAK:
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speculative = 0; // tbh don't really know what should happen here
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16'b1000XXXXX0000010, // C.JR
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16'b1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
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32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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speculative = 1;
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default:
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speculative = 0;
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@ -312,7 +323,7 @@ module testbench_busybear();
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//check things!
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if ((~speculative) && (PCF !== pcExpected)) begin
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$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
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// $stop;
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#10; $stop;
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end
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end
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end
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@ -338,10 +349,10 @@ module testbench_busybear();
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// if(MemWrite) begin
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// if(DataAdr === 84 & WriteData === 71) begin
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// $display("Simulation succeeded");
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// $stop;
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// #10; $stop;
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// end else if (DataAdr !== 80) begin
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// $display("Simulation failed");
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// $stop;
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// #10; $stop;
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// end
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// end
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// end
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