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https://github.com/openhwgroup/cvw.git
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Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
This commit is contained in:
Ross Thompson
parent
620f4a58d4
commit
0257c08641
9 changed files with 25 additions and 25 deletions
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@ -49,7 +49,7 @@ connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]} ]]
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connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/IEUAdrM[0]} {wallypipelinedsoc/hart/IEUAdrM[1]} {wallypipelinedsoc/hart/IEUAdrM[2]} {wallypipelinedsoc/hart/IEUAdrM[3]} {wallypipelinedsoc/hart/IEUAdrM[4]} {wallypipelinedsoc/hart/IEUAdrM[5]} {wallypipelinedsoc/hart/IEUAdrM[6]} {wallypipelinedsoc/hart/IEUAdrM[7]} {wallypipelinedsoc/hart/IEUAdrM[8]} {wallypipelinedsoc/hart/IEUAdrM[9]} {wallypipelinedsoc/hart/IEUAdrM[10]} {wallypipelinedsoc/hart/IEUAdrM[11]} {wallypipelinedsoc/hart/IEUAdrM[12]} {wallypipelinedsoc/hart/IEUAdrM[13]} {wallypipelinedsoc/hart/IEUAdrM[14]} {wallypipelinedsoc/hart/IEUAdrM[15]} {wallypipelinedsoc/hart/IEUAdrM[16]} {wallypipelinedsoc/hart/IEUAdrM[17]} {wallypipelinedsoc/hart/IEUAdrM[18]} {wallypipelinedsoc/hart/IEUAdrM[19]} {wallypipelinedsoc/hart/IEUAdrM[20]} {wallypipelinedsoc/hart/IEUAdrM[21]} {wallypipelinedsoc/hart/IEUAdrM[22]} {wallypipelinedsoc/hart/IEUAdrM[23]} {wallypipelinedsoc/hart/IEUAdrM[24]} {wallypipelinedsoc/hart/IEUAdrM[25]} {wallypipelinedsoc/hart/IEUAdrM[26]} {wallypipelinedsoc/hart/IEUAdrM[27]} {wallypipelinedsoc/hart/IEUAdrM[28]} {wallypipelinedsoc/hart/IEUAdrM[29]} {wallypipelinedsoc/hart/IEUAdrM[30]} {wallypipelinedsoc/hart/IEUAdrM[31]} {wallypipelinedsoc/hart/IEUAdrM[32]} {wallypipelinedsoc/hart/IEUAdrM[33]} {wallypipelinedsoc/hart/IEUAdrM[34]} {wallypipelinedsoc/hart/IEUAdrM[35]} {wallypipelinedsoc/hart/IEUAdrM[36]} {wallypipelinedsoc/hart/IEUAdrM[37]} {wallypipelinedsoc/hart/IEUAdrM[38]} {wallypipelinedsoc/hart/IEUAdrM[39]} {wallypipelinedsoc/hart/IEUAdrM[40]} {wallypipelinedsoc/hart/IEUAdrM[41]} {wallypipelinedsoc/hart/IEUAdrM[42]} {wallypipelinedsoc/hart/IEUAdrM[43]} {wallypipelinedsoc/hart/IEUAdrM[44]} {wallypipelinedsoc/hart/IEUAdrM[45]} {wallypipelinedsoc/hart/IEUAdrM[46]} {wallypipelinedsoc/hart/IEUAdrM[47]} {wallypipelinedsoc/hart/IEUAdrM[48]} {wallypipelinedsoc/hart/IEUAdrM[49]} {wallypipelinedsoc/hart/IEUAdrM[50]} {wallypipelinedsoc/hart/IEUAdrM[51]} {wallypipelinedsoc/hart/IEUAdrM[52]} {wallypipelinedsoc/hart/IEUAdrM[53]} {wallypipelinedsoc/hart/IEUAdrM[54]} {wallypipelinedsoc/hart/IEUAdrM[55]} {wallypipelinedsoc/hart/IEUAdrM[56]} {wallypipelinedsoc/hart/IEUAdrM[57]} {wallypipelinedsoc/hart/IEUAdrM[58]} {wallypipelinedsoc/hart/IEUAdrM[59]} {wallypipelinedsoc/hart/IEUAdrM[60]} {wallypipelinedsoc/hart/IEUAdrM[61]} {wallypipelinedsoc/hart/IEUAdrM[62]} {wallypipelinedsoc/hart/IEUAdrM[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 32 [get_debug_ports u_ila_0/probe9]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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@ -75,7 +75,7 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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@ -12,7 +12,7 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/I
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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@ -50,7 +50,7 @@ module lsu
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] MemAdrM,
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output logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] ReadDataM,
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@ -230,7 +230,7 @@ module lsu
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM);
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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// *** add generate to conditionally create hptw, lsuArb, and mmu
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// based on `MEM_VIRTMEM
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@ -238,7 +238,7 @@ module lsu
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.reset(reset),
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.SATP_REGW(SATP_REGW),
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.PCF(PCF),
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.MemAdrM(MemAdrM),
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.IEUAdrM(IEUAdrM),
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.ITLBMissF(ITLBMissF & ~PendingInterruptM),
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.DTLBMissM(DTLBMissM & ~PendingInterruptM),
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.MemRWM(MemRWM),
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@ -272,7 +272,7 @@ module lsu
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.MemRWM(MemRWM),
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.Funct3M(Funct3M),
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.AtomicM(AtomicM),
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.MemAdrM(MemAdrM),
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.IEUAdrM(IEUAdrM),
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.IEUAdrE(IEUAdrE[11:0]),
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.CommittedM(CommittedM),
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.PendingInterruptM(PendingInterruptM),
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@ -295,7 +295,7 @@ module lsu
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation(DisableTranslation),
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.PAdr(MemPAdrMtoDCache),
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.VAdr(MemAdrM),
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.VAdr(IEUAdrM),
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.Size(Funct3MtoDCache[1:0]),
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.PTE(PTE),
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.PageTypeWriteVal(PageType),
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@ -356,7 +356,7 @@ module lsu
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.AtomicM(AtomicMtoDCache),
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.IEUAdrE(MemAdrEtoDCache),
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.MemPAdrM(MemPAdrM),
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.VAdr(MemAdrM[11:0]),
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.VAdr(IEUAdrM[11:0]),
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.WriteDataM(WriteDataM),
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.ReadDataM(ReadDataM),
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.DCacheStall(DCacheStall),
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@ -38,7 +38,7 @@ module lsuArb
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [1:0] AtomicM,
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input logic [`XLEN-1:0] MemAdrM,
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input logic [`XLEN-1:0] IEUAdrM,
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input logic [11:0] IEUAdrE,
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input logic StallW,
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input logic PendingInterruptM,
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@ -67,7 +67,7 @@ module lsuArb
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logic [2:0] PTWSize;
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logic [`PA_BITS-1:0] TranslationPAdrM;
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logic [`XLEN+1:0] MemAdrMExt;
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logic [`XLEN+1:0] IEUAdrMExt;
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// multiplex the outputs to LSU
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assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
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@ -82,8 +82,8 @@ module lsuArb
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flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM); // delay TranslationPAdrM by a cycle
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assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
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assign MemAdrMExt = {2'b00, MemAdrM};
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assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0];
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assign IEUAdrMExt = {2'b00, IEUAdrM};
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assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
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assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
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assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
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// always block interrupts when using the hardware page table walker.
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@ -34,7 +34,7 @@ module hptw
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(
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input logic clk, reset,
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input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
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input logic [`XLEN-1:0] PCF, MemAdrM, // addresses to translate
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input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
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input logic ITLBMissF, DTLBMissM, // TLB Miss
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input logic [1:0] MemRWM, // 10 = read, 01 = write
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input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
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@ -82,7 +82,7 @@ module hptw
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assign TLBMiss = (DTLBMissM | ITLBMissF);
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// Determine which address to translate
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assign TranslationVAdr = DTLBWalk ? MemAdrM : PCF;
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assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
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assign CurrentPPN = PTE[`PPN_BITS+9:10];
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// State flops
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@ -56,7 +56,7 @@ module privileged (
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input logic StoreMisalignedFaultM,
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input logic TimerIntM, ExtIntM, SwIntM,
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input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
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input logic [4:0] SetFflagsM,
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// Trap signals from pmp/pma in mmu
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@ -231,7 +231,7 @@ module privileged (
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.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
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.STATUS_MIE, .STATUS_SIE,
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.PCM,
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.InstrMisalignedAdrM, .MemAdrM,
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.InstrMisalignedAdrM, .IEUAdrM,
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.InstrM,
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.InstrValidM, .CommittedM,
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.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
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@ -39,7 +39,7 @@ module trap (
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
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input logic STATUS_MIE, STATUS_SIE,
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input logic [`XLEN-1:0] PCM,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
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input logic [31:0] InstrM,
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input logic InstrValidM, CommittedM,
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output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
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@ -157,12 +157,12 @@ module trap (
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always_comb
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if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
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else if (LoadMisalignedFaultM) NextFaultMtvalM = MemAdrM;
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else if (StoreMisalignedFaultM) NextFaultMtvalM = MemAdrM;
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else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
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else if (StoreMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
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else if (BreakpointFaultM) NextFaultMtvalM = PCM;
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else if (InstrPageFaultM) NextFaultMtvalM = PCM;
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else if (LoadPageFaultM) NextFaultMtvalM = MemAdrM;
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else if (StorePageFaultM) NextFaultMtvalM = MemAdrM;
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else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM;
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else if (StorePageFaultM) NextFaultMtvalM = IEUAdrM;
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else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
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else NextFaultMtvalM = 0;
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endmodule
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@ -123,7 +123,7 @@ module wallypipelinedhart (
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] IEUAdrE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
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logic [`XLEN-1:0] ReadDataW;
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logic CommittedM;
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@ -245,7 +245,7 @@ module wallypipelinedhart (
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.SquashSCW,
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//.DataMisalignedM(DataMisalignedM),
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.IEUAdrE, .MemAdrM, .WriteDataM,
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.IEUAdrE, .IEUAdrM, .WriteDataM,
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.ReadDataM, .FlushDCacheM,
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// connected to ahb (all stay the same)
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.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
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@ -343,7 +343,7 @@ module wallypipelinedhart (
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.LoadMisalignedFaultM, .StoreMisalignedFaultM,
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.TimerIntM, .ExtIntM, .SwIntM,
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.MTIME_CLINT, .MTIMECMP_CLINT,
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.InstrMisalignedAdrM, .MemAdrM,
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.InstrMisalignedAdrM, .IEUAdrM,
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.SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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