github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-27 17:01:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix new python lint errors discovered

Browse source
This commit is contained in:
Jordan Carlin 2025-04-08 20:53:25 -07:00
parent 5274723863
commit 0342e719b4
No known key found for this signature in database
6 changed files with 51 additions and 49 deletions
Download patch file Download diff file Expand all files Collapse all files

1
.pre-commit-config.yaml
View file

@ -6,6 +6,7 @@
# See https://pre-commit.com for more information
# See https://pre-commit.com/hooks.html for more hooks
exclude: addins/
minimum_pre_commit_version: "4.0.0"
repos:
# Standard pre-commit hooks

3
.ruff.toml
View file

@ -1,6 +1,5 @@
# Lint all .py files and extra python scripts without extensions
include = ["*.py", "bin/wsim", "bin/regression-wally", "bin/iterelf", "sim/vcs/run_vcs"]
exclude = ["addins/*", "tests/fp/quad/fpdatasetgen.py"]
exclude = ["addins/*"]
# Target oldest version of Python used (Python 3.9 for Ubuntu 20.04 LTS)
target-version = "py39"

13
fpga/generator/probe
View file

@ -26,6 +26,7 @@
import sys
def usage():
print("Usage: ./probes name width probenum")
@ -54,19 +55,19 @@ def convertLine(x):
return tuple(temp)
def probeBits( probe ):
str = ''
string = ''
if (probe[1] > 1):
for i in range(probe[1]):
if i != (probe[1]-1):
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = f'{{{probe[0]}}}'
string = f'{{{probe[0]}}}'
return str
return string
def printProbe( probe, i ):
bits = probeBits(probe)
@ -93,5 +94,3 @@ def main(args):
if __name__ == '__main__':
main(sys.argv[1:])

11
fpga/probe
View file

@ -27,6 +27,7 @@
import sys
def usage():
print("Usage: ./probes name width probenum")
exit(1)
@ -37,19 +38,19 @@ def convertLine(x):
return tuple(temp)
def probeBits( probe ):
str = ''
string = ''
if (probe[1] > 1):
for i in range(probe[1]):
if i != (probe[1]-1):
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = f'{{{probe[0]}}}'
string = f'{{{probe[0]}}}'
return str
return string
def printProbe( probe, i ):
bits = probeBits(probe)

11
fpga/proberange
View file

@ -27,6 +27,7 @@
import sys
def usage():
print("Usage: ./probes list_of_probes outfile")
@ -56,19 +57,19 @@ def convertLine(x):
return tuple(temp)
def probeBits( probe ):
str = ''
string = ''
if (probe[1] > 1):
for i in range(probe[1]):
if i != (probe[1]-1):
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = f'{{{probe[0]}}}'
string = f'{{{probe[0]}}}'
return str
return string
def printProbe( probe,):
bits = probeBits(probe)

11
fpga/probes
View file

@ -27,6 +27,7 @@
import sys
def usage():
print("Usage: ./probes list_of_probes outfile")
@ -55,19 +56,19 @@ def convertLine(x):
return tuple(temp)
def probeBits( probe ):
str = ''
string = ''
if (probe[1] > 1):
for i in range(probe[1]):
if i != (probe[1]-1):
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = str + f"{{{probe[0]}[{i}]}} "
string = string + f"{{{probe[0]}[{i}]}} "
else:
str = f'{{{probe[0]}}}'
string = f'{{{probe[0]}}}'
return str
return string
def printProbe( probe, i ):
bits = probeBits(probe)