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Update riscv-arch-test

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Jordan Carlin 2025-02-15 20:44:55 -08:00
parent 1053d81f48
commit 048d2312af
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2 changed files with 5 additions and 5 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit eeffdf802c117f592b30e380b59caf48da384e76 Subproject commit 3baa17a888cd6b5a8ca78ada757783ae0c061b3a

8
testbench/tests.vh
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@ -250,6 +250,9 @@ string arch32vm_sv32[] = '{
"rv32i_m/vm_sv32/src/satp_access_tests.S", "rv32i_m/vm_sv32/src/satp_access_tests.S",
"rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S", "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
"rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S", "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S", "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S", "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S", "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
@ -267,10 +270,7 @@ string arch32vm_sv32[] = '{
"rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S", "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S", "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S", "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S", "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S"
"rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
}; };
string arch64priv[] = '{ string arch64priv[] = '{